High speed Vedic multiplier design and implementation on FPGA (original) (raw)
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FPGA Implementation of Low Power and High Speed Vedic Multiplier using Vedic Mathematics
A high speed processor depends greatly on the multiplier as it is one of the key hardware blocks in most digital signal processing system as well as in general processors. This paper proposes the design of 8x8 bit Vedic multiplier based on vertical and crosswise structure of Ancient Indian Vedic Mathematics. The proposed architecture is for two 8-bit numbers, the multiplier and multiplicand each arc grouped as 4-bit numbers; so that it decomposes into 4x4 multiplication modules. This gives chance for modular design where smaller blocks can be used to design the bigger one. Further, the VHDL coding of Urdhava Tiryakbhyam sutra for 8x8 bits multiplication and their FPGA implementation by Xilinx Synthesis Tool have been done.
2021
This paper is regarding the design and analysis of an efficient 8×8 Vedic multiplier by the principle of Vedic mathematics [1]. Here, a unique Vedic multiplier architecture is adapted, which is not based on the regular method of multiplication (addition, shifting). The design is as per the "Urdhwa-Tiryakbhyam Sutra" of Vedic mathematics. Two numbers (binary of 8-bit each) are multiplied using the methodology of this principle/sutra. "Urdhwa-Tiryakbhyam" means "vertically and crosswise", wherein the partial products are computed at once, thus lessening the delay and hence making the multiplication faster. This 8 by 8 bit multiplier is coded in Verilog HDL and tested on a DE10-lite FPGA kit.
Fpga Implementation Of High Speed Vedic Multipliers
2012
High speed and efficient multipliers are required in day to day complex computational circuits like digital signal processing, cryptography algorithms and high speed processors. Among various methods of multiplication, recently Vedic multipliers are being more efficient. This paper presents a design of high speed 4X4 bit Vedic multiplier architectures based on two different Vedic sutras namely, Urdhva-Triyag and Nikhilam. These sutras meant for faster mental calculation. Among these two sutras Urdhva-Triyag is more efficient than Nikhilam and other multipliers with respect to speed. The most significant aspect of Urdhva-Triyag sutra is that, the developed multiplier generates all partial products in one step. High speed adders are used in the architecture instead of conventional Ripple carry adders thereby reducing the delay further. In Nikhilam multiplier architecture Urdhva-Triyag sutra is used for more efficiency. The Vedic multiplier architectures are coded in Verilog HDL and synthesized using Xilinx ISE 13.3. The proposed multiplier architectures are targeted to Spartan 3E FPGA. Finally the results are compared with conventional multipliers to show the efficiency in terms of speed.
Novel High Speed Vedic Mathematics Multiplier using Compressors
With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. In this paper, we introduce a novel architecture to perform high speed multiplication using ancient Vedic maths techniques. A new high speed approach utilizing 4:2 compressors and novel 7:2 compressors for addition has also been incorporated in the same and has been explored. Upon comparison, the compressor based multiplier introduced in this paper, is almost two times faster than the popular methods of multiplication. With regards to area, a 1% reduction is seen. The design and experiments were carried out on a Xilinx Spartan 3e series of FPGA and the timing and area of the design, on the same have been calculated.
IJERT-Fpga Implementation Of High Speed Vedic Multipliers
International Journal of Engineering Research and Technology (IJERT), 2012
https://www.ijert.org/fpga-implementation-of-high-speed-vedic-multipliers https://www.ijert.org/research/fpga-implementation-of-high-speed-vedic-multipliers-IJERTV1IS10128.pdf High speed and efficient multipliers are required in day to day complex computational circuits like digital signal processing, cryptography algorithms and high speed processors. Among various methods of multiplication, recently Vedic multipliers are being more efficient. This paper presents a design of high speed 4X4 bit Vedic multiplier architectures based on two different Vedic sutras namely, Urdhva-Triyag and Nikhilam. These sutras meant for faster mental calculation. Among these two sutras Urdhva-Triyag is more efficient than Nikhilam and other multipliers with respect to speed. The most significant aspect of Urdhva-Triyag sutra is that, the developed multiplier generates all partial products in one step. High speed adders are used in the architecture instead of conventional Ripple carry adders thereby reducing the delay further. In Nikhilam multiplier architecture Urdhva-Triyag sutra is used for more efficiency. The Vedic multiplier architectures are coded in Verilog HDL and synthesized using Xilinx ISE 13.3. The proposed multiplier architectures are targeted to Spartan 3E FPGA. Finally the results are compared with conventional multipliers to show the efficiency in terms of speed.
Review on Design Approach for FPGA Implementation of 16-Bit Vedic Multiplier
In this paper, a high speed and low power 16x16 Vedic Multiplier is designed by using low power and high speed modified carry select adder. Modified Carry Select Adder employs a newly incremented circuit in the intermediate stages of the Carry Select Adder (CSA) which is known to be the fastest adder among the conventional adder structures. A Novel technique for digit multiplication namely Vedic multiplication has been introduced which is quite different from normal multiplication by shift and addition operations. Normally a multiplier is a key block in almost all the processors and also introduces high delay block and also a major power dissipation source. This paper presents a new design methodology for less delay and less power efficient Vedic Multiplier based up on ancient Vedic Mathematic techniques. This paper presents a technique for N×N multiplication is implemented and gives very less delay for calculating multiplication results for 16×16 Vedic multiplier. In this paper, the main goal is to design the high speed and low power and area efficient Vedic multiplier based on the crosswise and vertical algorithm. Comparisons with existing conventional fast adder architectures have been made to prove its efficiency. The performance analysis shows that the proposed architecture achieves three fold advantages in terms of delay-area-power. The synthesis results of the Vedic multiplier has compared with the booth, array multiplier by different technologies. Booth multipliers are generally used for multiplication purposes. Booth Encoder, Wallace Tree, Binary Adders and Partial Product Generator are the main components used for Booth multiplier architecture. Booth multiplier is mainly used for 2 applications are to increase the speed by reduction of the partial products and also by the way that the partial products to be added. The Vedic mathematics mainly reduces the complex typical calculations in to simpler by applying sutras as stated above. These Vedic mathematic techniques are very efficient and take very less hardware to implement. These sutras are mainly used for multiplication of two decimal numbers and we extend these sutras for binary multiplications. Multiplexer is also called Universal element or Data Selector. A Multiplexer has of 2^n inputs have n select lines Basically MUX operation based on the select lines. Depending upon the select line the input is Send to the output. Multiplexers used to increase the amount of data that can be sent over the network. The values of 4 bit can be taken and remaining can be obtained from the next blocks. Like that we will obtain totally sixteen outputs and those are outputs of the sixteen bit addition.
Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques
This paper proposed the design of high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have been modified to improve performance. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. The work has proved the efficiency of Urdhva Triyagbhyam-Vedic method for multiplication which strikes a difference in the actual process of multiplication itself. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels using Karatsuba algorithm with the compatibility to different data types. Urdhva tiryakbhyam Sutra is most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers, either small or large. Further, the Verilog HDL coding of Urdhva tiryakbhyam Sutra for 32x32 bits multiplication and their FPGA implementation by Xilinx Synthesis Tool on Spartan 3E kit have been done and output has been displayed on LCD of Spartan 3E kit. The synthesis results show that the computation time for calculating the product of 32x32 bits is 31.526 ns.
Design And Implementation Of High Speed Vedic Multiplier
Vedic mathematics is the ancient Indian system of mathematics. This paper proposed the design oh high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that has been modified to improve performance. Multipliers play a major role in processors and in many computational systems. The speed of these systems greatly depends on the speed of its multipliers. In order to enhance the speed of the systems the faster and efficient multipliers should be employed. Vedic Multiplier is one of the best solution which is capable of performing the quicker multiplications by eliminating the unwanted steps in the multiplication process. Vedic Multiplier deals with a total of sixteen sutras or algorithms for predominantly logical operations. In this paper it is used for designing a high speed, low power 4X4 multiplier. In the proposed design we have reduced the number of logic levels, thus reducing the logic delay. The proposed system is design using VHDL and it is implemented through Xilinx 8.1.
Design and Implementation of High Speed Vedic Multiplier using Brent Kung Adder on FPGA
This paper presents the design and implementation of high speed Vedic multiplier (Urdhva Tiryagbhyam algorithm) using parallel prefix adders on Virtex 6 FPGA. Brent kung adder, which is a parallel prefix adder is used for addition of partial products. Use of Brent kung adder will improve the speed of addition but hardware complexity will increase. A 16-bit and 8-bit vedic multiplier is designed using Verilog Hardware Description Language and synthesized on XiIlinx Design Suite 14.7 and simulated using Isim simulator. Compared to existing designs the proposed design is having significant improvement in delay. The proposed 16-bit/8bit vedic multiplier is having 37% and 32% improvement in delay respectively, compared to an existing recent design.
Speed Comparison of 16x16 Vedic Multipliers
International Journal of Computer Applications, 2011
The paper presents the concepts behind the "Urdhva Tiryagbhyam Sutra" and "Nikhilam Sutra" multiplication techniques. It then shows the architecture for a 16×16 Vedic multiplier module using Urdhva Tiryagbhyam Sutra. The paper then extends multiplication to 16×16 Vedic multiplier using "Nikhilam Sutra" technique. The 16×16 Vedic multiplier module using Urdhva Tiryagbhyam Sutra uses four 8×8 Vedic multiplier modules; one 16 bit carry save adders, and two 17 bit full adder stages. The carry save adder in the multiplier architecture increases the speed of addition of partial products. The 16×16 Vedic multiplier is coded in VHDL, synthesized and simulated using Xilinx ISE 10.1 software. This multiplier is implemented on Spartan 2 FPGA device XC2S30-5pq208. The performance evaluation results in terms of speed and device utilization are compared with earlier multiplier architecture. The proposed design has speed improvements as compared to multiplier architecture presented in [5].