Considering variation and aging in a full chip design methodology at system level (original) (raw)

Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn), 2014

Abstract

ABSTRACT We present a new system-level design methodology enabling the consideration of process variations and degradation due to aging in early stages of the design process. By mapping an executable system specification to SoC processing, communication and memory components in combination with component wise timing and power characterization with a source-level backannotation, we enable efficient full SoC power and temperature over time simulations. Based on the resulting temporal and spatial power and temperature distribution we use a high-level multiphysics simulation to assess the impact of degradation and aging. We evaluate our approach using an ARM7 based SoC design.

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