Implementation of sub-nanosecond time-to-digital convertor in field-programmable gate array: applications to time-of-flight analysis in muon radiography (original) (raw)
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The characterization and application of a low resource FPGA-based time to digital converter
Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2014
Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of "off-the-shelf" TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct γγ physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a 32 channel TDC with a precision of 255 ps and low nonlinearity effects along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. The TDC is based on a low resources occupancy technique: the 4 Â Oversampling technique which, in this work, is pushed to its best resolution and its performances were exhaustively measured.
Performance and area tradeoffs in space-qualified FPGA-based time-of-flight systems
2009 9th International Conference on Electronic Measurement & Instruments, 2009
This paper introduces four FPGA-based designs for radiation-tolerant time-of-flight (TOF) systems for sub-atomic particles: Snapshot, Vernier, Fast-Clocking and Hybrid designs. The designs measure TOFs ranging from 0 to 240 ns and are compared based on resolution, thermal performance, FPGA I/O pin usage and area, particle processing rate, and power consumption. All designs are implemented and tested on an Actel ProASIC 3E A3PE1500 FPGA using only the features available on the radiationtolerant Actel RTAX 2000 S/SL. The designs achieve resolutions of 130 ps to 25 ns and particle rates of 1.63 to 40 MHz, use from 0.02% to 7.5% of the FPGA area, and consume from 396 to 448 mW. The TOF measurements of the Fast-Clocking Design show no thermal variation across the ranges of-25°C to 55°C. The other three designs vary linearly with temperature, but this variation can be calibrated using a temperature sensor. All four designs offer a flexible, inexpensive TOF measurement system that can be implemented across a broad range of FPGAs.
Fast Time-Of-Flight System for Muon Cooling Experiments*
2011
A new generation of large-area, low cost time-of-flight detectors with time resolutions ≤ 10 ps and space resolutions ≤ 1 mm is being developed for use in nuclear and particle physics experiments, as well as for medical and industrial applications. Such detectors are being considered for use in muon cooling channel tests. Designs and fabrication of prototype planes and associated readout electronics are described. Results of simulations of time and space resolutions are presented.
Experimental results with TOFPET2 ASIC for time-of-flight applications
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2018
We present the experimental results obtained with TOFPET2, a readout and digitization ASIC for radiation detectors using Silicon Photomultipliers. The circuit is designed in CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in PET or other applications. The chip has quadbuffered TDCs and charge integration ADCs in each channel. The chip tape-out was done in September 2016 and first tests started in beginning March 2017. Coincidence Time Resolution (CTR) of 164 ps FWHM has been measured with 22 Na point source. The energy resolution achieved for the 511 keV peak is 10.5% FWHM.
Multichannel FPGA-Based Data-Acquisition-System for Time-Resolved Synchrotron Radiation Experiments
IEEE Transactions on Nuclear Science, 2017
The aim of this contribution is to describe our recent development of a novel compact FPGA-based data acquisition system for use with multi-channel X-ray detectors at synchrotron radiation facilities. The system is designed for time resolved counting of single photons arriving from severalcurrently 12-independent detector channels simultaneously. Detector signals of at least 2.8 ns duration are latched by asynchronous logic and then synchronized with the system clock of 100 MHz. The incoming signals are subsequently sorted out into 10000 time-bins where they are counted. This occurs according to the arrival time of photons with respect to the trigger signal. Repeatable mode of triggered operation is used to achieve high statistic of accumulated counts. The time-bin width is adjustable from 10 ns to 1 ms. In addition, a special mode of operation with 2 ns time resolution is provided for two detector channels. The system is implemented in a pocket-size FPGAbased hardware of 10 cm x 10 cm x 3 cm and thus can easily be transported between synchrotron radiation facilities. For setup of operation and data read-out the hardware is connected via USB interface to a portable control computer. Data acquisition applications are provided in both LabVIEW® and MATLAB® environments.
Nuclear Instruments & Methods in Physics Research Section a-Accelerators Spectrometers Detectors and Associated Equipment, 2013
In order to reconstruct γγ physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a Time to Digital Converter (TDC) with 625 ps resolution (LSB) along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. We will describe briefly the architecture of the TDC and of the Data AcQuisition (DAQ) system. Some more details will be provided about the zero-suppression algorithm used to reduce the data throughput.
Digital Signal Processing for Particle Detectors in Front-End Electronics
2014
The Large Hadron Collider (LHC) at CERN is currently being started up after a long shutdown. Another similar maintenance and upgrade period is due to take place in a few years. The luminosity and maximum beam energy will be increased after the shutdowns. Many upgrade projects stem from the increased demands from the changed environment and the opportunity of installation work during the shutdowns. The CMS GEM collaboration proposes to upgrade the muon system in CMS experiment by adding Gaseous Electron Multiplier (GEM) chambers. The new GEM-detectors need new Front-End electronics. There are two parallel development branches for mixed-signal ASICs; one comes with analog signal processing (VFAT3-chip) and another with analog and digital signal processing (GdSP-chip). This Thesis covers the development of the digital signal processing for the GdSP-chip. The design is described on algorithm level and with block diagrams. The signal originating in the triple GEM-detector sets special challenges on the signal processing. The time constant in the analog shaper is programmable due to irregularities in the GEM-signal. This in turn poses challenges for the digital signal processing. The pulse peaking time and signal bandwidth depend on the choice made for the time constant. The basic signal processing techniques and needs are common for many detectors. Most of the digital signal processing has shared requirements with an existing, well-tested Front-End chip. Time pick-off and trigger production was not included in these shared tasks. Several time pick-off methods were considered and compared with simulations. The simulations were performed first using Simulink running on Matlab and then on Cadence tools using Verilog hardware description language. Time resolution is an important attribute determined jointly by the detector and the signal processing. It is related to the probability to associate the measured pulse with the correct event. The effect of the different time pick-off methods on time resolution was compared with simulations. Only the most promising designs were developed further. Constant Fraction Discriminator and Pulse Recognition, the two most promising algorithms, were compared against analog Constant Fraction Discriminator and Time over Threshold time pick-off methods. The time resolutions obtained with noiseless signal were found to be comparable. At least in gas detector applications digital signal processing should not be ruled out of fear for deteriorated time resolution. The proposed digital signal processing chain for GdSP includes Baseline Correction, Digital Shaper, Integrator, Zero Suppression and Bunch Crossing Identification. The Baseline Correction includes options for using fixed baseline removal and moving average filter. In addition it contains a small memory, which can be used as test signal input or as look-up-table et cetera. Pole-zero cancellation is proposed for digital shaping. The integrator filters high frequency noise. The Constant Fraction Discriminator was found optimal for Bunch Crossing Identification.
2002
This paper presents an integrated time to digital converter (TDC) with a bin size adjustable in the range of 125 to 175 ps and a differential nonlinearity of 70.3%. The TDC has four channels. Its architecture has been optimized for the readout of imaging detectors in use at Synchrotron Radiation facilities. In particular, a built-in logic flags piled-up events. Multi-hit patterns are also supported for other applications. Time measurements are extracted off chip at the maximum throughput of 40 MHz. The dynamic range is 14 bits. It has been fabricated in 0.8 mm BiCMOS technology. Time critical inputs are PECL compatible whereas other signals are CMOS compatible. A second application specific integrated circuit (ASIC) has been developed which translates NIM electrical levels to PECL ones. Both circuits are used to assemble board level TDCs complying with industry standards like VME, NIM and PCI. r
A multi-channel time-to-digital converter chip for drift chamber readout
IEEE Transactions on Nuclear Science, 1996
A complete, multi-channel, timing and amplitude measurement IC for use in drift chamber applications is described. By targeting specific resolutions, i.e. 6-bits of resolution for both time and amplitude, area and power can be minimized while achieving the proper level of measurement accuracy. Time is digitized using one eight channel TDC comprised of a delay locked loop and eight sets of latches and encoders. Amplitude (for dE/dx) is digitized using a dual-range FADC for each channel. Eight bits of dynamic range with six bits of accuracy are achieved with the dual-range. The timing and amplitude information is multiplexed into one DRAM (Dynamic Random Access Memory) trigger latency buffer. Interesting events are then transferred into an SRAM (Static Random Access Memory) readout buffer before the latency time has expired. The design has been optimized to achieve the requisite resolution using the smallest area and lowest power. The circuit has been implemented in a 0.8u, triple metal CMOS process. The TDC sub-element has been measured to have better than 135 ps time resolution and 35 ps jitter. The DRAM has a measured cycle time of 80 MHz.