Design Methodologies Based on Hardware Description Languages (original) (raw)
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CONCISE METHODOLGY FOR DEVELOPMENT OF COMPLEX DIGITAL ELECTRONIC SYSTEMS
ijetrm journal
Development of simple digital electronic circuits can be easily done using combinational logic theory such as Boolean Algebra and Karnaugh Maps, along with tools such as Xilinx Schematic Editor. Even medium-sized systems can be developed this way. What about complex digital electronics systems? Utilizing the same procedure may be tedious and hence will be best done using a more effective and structured procedure, along with use of hardware descriptive languages. This paper therefore presents a concise methodology for the development of complex digital electronics systems. The paper will focus on all aspects including the specification, formal specification and modelling of the system, the choice of development platforms, hardware description, and even the formal verification and validation of such system. An example will be used as the basis of the formal specification and modelling aspect of the paper to ensure that readers can quickly absorb the material presented. The author intends for the contents of this paper to be informative and expects that developing digital design engineers find this methodology useful in development of systems they attempt to pursue.
A structural design language for computer aided design of digital systems
1977
In this report a language (SDL) for describing structural properties of digital systems will be presented. SDL can be used at all levels of 4 the design process i.e. from the system level down to the circuit level. The language is intended as a complement to existing computer hardware description languages, which emphasize behavioural description. The language was motivated partly by the nature of the design process. INDEX TERMS: Computer-aided design, hardware description languages, c design automation, structural design language, design methodology.
Contemporarily, owing to astronomical advancements in the very large scale integration (VLSI) market segments, hardware engineers are now focusing on how to develop their new digital system designs in programmable languages like very high speed integrated circuit hardware description language, (VHDL) and Verilog and consequently target it to Complex programmable logic devices (CPLDs) and Field programmable gate arrays (FPGAs). This paper focuses on using VHDL, to design an application specific integrated circuit (ASIC) liquid dispenser controller system while targeting the device independent architecture (Ultra 3700 CPLD series) for synthesis ,optimization and fitting to realize the design. The ASIC controller has two bin cans to dispense regular and diet drinks. The system dispenses a drink if the user activates a button for that drink and at least one can is available. A refill signal appears when both bins are empty. Activating a reset signal informs the system that the machine has been refilled and the bins are full. The design methodology is presented with other details in the body of this paper.
Design of digital circuits on the basis of hardware templates
2003
This paper presents a technique for the design of digital systems on the basis of reusable hardware templates (HT), which are circuits with modifiable functionality that might be customized to satisfy requirements of target applications, such as a highly optimized implementation of the selected problem-specific operations. It demonstrates how HTs can be modeled in software with the aid of suggested C++ classes and implemented in hardware (in FPGA in particular). It is shown that the desired functionality of HT-based digital systems might be provided through some changes to the behavior of reprogrammable finite state machines (RFSM) that are considered to be primary customizable blocks. The paper describes a parameterizable VHDL code of RFSM and demonstrates how the respective circuit can be implemented in FPGA.
IEEE Circuits and Devices Magazine, 2004
pplications requiring cost-effective, low-power digital signal processing (DSP) are prevalent not only in military and aerospace systems but also in numerous commercial products. Many of these systems need to be miniaturized so they can be highly mobile or portable. The resulting severe size, weight, and power requirements for DSP electronics can only effectively be realized in the form of advanced application-specific integrated circuits (ASICs) implementing mission-specific architectures. As shown in Figure 1, mission-specific ASIC architectures can realize 100× improvement in giga operations per second per watt (GO/s/W) for a typical DSP algorithm versus implementation in general purpose DSP chips . (An operation is defined by most ASIC designers as a 16 × 16-b multiplication. However, this definition is not universal, so in this article we report improvements normalized to a baseline to factor out this term.) Programmable logic chips are insufficient to achieve the desired throughput and power specifications for these applications.
An Approach to the Design of Specific Hardware Circuits from C Programs
J. Inf. Sci. Eng., 2018
This article presents an approach that helps convert a given C program into a hardware implementation for a digital circuit design. Based on and extended from the concept of hierarchical finite-state machines (HFSMs), four built-in HFSM templates, namely Seq, Par, Loop and Atomic, are proposed and used as the elementary components of a hardware design. A guideline on the refinement of a C program is also proposed; the refined C functions are compiled into HFSMs that in turn generate synthesizable hardware description language (HDL) code as the final design. A set of HFSMs is viewed as an intermediate representation between C and HDL and can be functionally simulated. Two modeling levels, i.e. cycle-accurate and cycle-approximated, are supported. A compilation technique based on syntax-directed translations is used to automate the proposed approach. Experimental results on several well-known algorithmic benchmarks show the effectiveness of the proposed approach.
2008 11th IEEE International Power Electronics Congress, 2008
This paper presents a research line oriented to develop methodologies that takes advantage of hardware description languages in order to simplify the design of power converters that employ digital control techniques. The methodology focuses on setting the adequate communications among subsystems in order to simplify the change of the levels of abstraction of the subsystem's models (from the conceptual level to the actual electric + synthesizable code). Changing the level of abstraction in the design process pretends: first to provide useful models at early designing steps; second, to optimize the simulation of the system, and at same time optimize the verification step.
Register-Transfer-Level Design for Application-Specific Integrated Circuits
Energy Systems in Electrical Engineering, 2020
Over the years, a rapid growth has been witnessed in electronics semiconductor industry because of the huge demand for system-level designs. System-level designs are prominently used for various applications such as high-performance computing, controls, telecommunications, image and video processing, consumer electronics and others. Hence to accomplish such applications using very largescale integration (VLSI) design, it is recommended to have an efficient registertransfer-level (RTL) design abstraction, as it can provide a low power and highperformance outcome (Wu and Liu in IEEE Trans Very Large Scale Integr (VLSI) Syst 6:707-718, Wu and Liu 1998). In digital integrated circuit (IC) design, RTL models a synchronous digital circuit in terms of the flow of digital signals or data between hardware registers and the logical operations performed on these signals. RTL abstraction is used in hardware description languages (HDLs) to create highlevel representations of a circuit (Chinedu et al. in 3rd IEEE international conference on adaptive science and technology (ICAST 2011). IEEE, pp 262-267, Chinedu et al. 2011). From these lower-level representations, ultimately actual circuitry can be derived. Design at the RTL level is a typical practice in modern digital system designs. This chapter mainly focuses on design of RTLs for application-specific integrated circuits (ASICs) and how it differs for field-programmable gate arrays (FPGAs). The examples and modules discussed in this chapter are written in HDL, viz. Verilog language.
Hardware modeling and top-down design using VHDL
Masters Thesis, 1991
As digital designs grow more and more complex, some method of controlling this complexity must be used in order to reduce the.number of errors and the time spent on a design. VHDL (Very High Speed Integrated Circuit Hardware Description Language) promises to ease the design and verification of complex digital circuits by encouraging the use of top-down design. This thesis demonstrates how VHDL, combined with a top-down design methodology, enables the designer to specify and verify a digital design faster and with fewer errors. The scoreboard, a section of hardware in the Charles Stark Draper Laboratory's Fault Tolerant Parallel Processor, is used as an example to demonstrate the utility of VHDL. The scoreboard is responsible for message processing within the FTPP and thus has a critical effect on performance. It also represents the most significant risk of any component in the FTPP. The use of VHDL has the potential for ensuring an optimal scoreboard design with minimal errors and an improved design time.