Designing Dynamic Carry Skip Adders: Analysis and Comparison (original) (raw)
Related papers
International Journal of Science and Research (IJSR), 2016
The portable equipments such as cellular phones, Personal Digital Assistant (PDA), and notebook personal computer, arise the need of effective circuit area and power efficient VLSI circuits. Addition is the most common and often used arithmetic operation in digital computers and also, it serves as a building block for synthesis all other arithmetic operations. Low-power and high-speed adder cells (like carry skip adder) are used in battery operation based devices. Now the biggest challenge is reduction of adder power consumption and delay while maintaining the high performance in different types of circuit design. In conventional carry skip adder the multiplexer is used as a skip logic that provides a better performance and performs an efficient operation with the minimum circuitry. Even though, it affords a significant advantages there may be a large critical path delay revealed by the multiplexer and also it containing twelve transistors that leads to increase of area usage and power consumption. The proposed method uses compound gates such as AOI and OAI as skip logic in the design that leads to decrease area usage, delay and power consumption, also in addition the parallel prefix adder is included to attain further reduction of power. The design is coded in VHDL and simulated in ModelSim and its area, delay and power are analyzed using Xilinx_ISE 9.2i.
— In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders using a 45-nm static CMOS technology for a wide range of supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power–delay product was the lowest among the structures considered in this paper, while its energy–delay product was almost the same as that of the Kogge–Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latest works in this field while having a reasonably high speed. Index Terms— Carry skip adder (CSKA), energy efficient, high performance, hybrid variable latency adders, voltage scaling.
2014
Abstract. The most timing critical part of logic design usually contains one or more arithmetic operations,in which addition is commonly involved. In VLSI applications, area, delay and power are the important factorswhich must be taken into account in the design of a fast adder [1]. The paper attempts to examine the featuresof certain adder circuits which promise superior performance compared to existing circuits. The advantagesof these circuits are low-power consumption, a high degree of regularity and simplicity. The main emphasisis on reducing power consumption in these circuits and also helps in better (power delay product) PDP [3].The carry-skip adder proposed here reduces the time needed to propagate the carry by skipping over groups ofconsecutive adder stages, is known to be comparable in speed to the carry look-ahead technique while it usesless logic area and less power [1]. Carry Skip Adder (CSA) is simulated for different structures such as 2, 4 and8-blocks. Simulation res...
A Review of 1-Bit Full Adder Design Using Different Dynamic CMOS Techniques
2021
The Domino CMOS Logic Circuits are famously utilized in Very Large Scale Integrated (VLSI) structure. To design a VLSI circuit having low power and fast execution or high speed is the most testing task. By and by, one of the main goals is low power VLSI circuits with high speed. Full Adders are mainly used in various circuits which can perform various errands like development, duplication, division etc. In this manner it will diminish the force usage in full adders expects an enormous part of VLSI circuits having low power. In this paper, domino logic is used to manage a stable, particularly improved response for two constraints in full adder circuits i.e. power and delay. We review the Power, Delay and Power Delay Product (PDP) of 22T Domino Full Adder, 27T Domino Full Adder and 28T Static Full Adder. In this we also review these 3 circuit on the basis of different technology nodes or the feature length i.e. 45nm, 90nm and 180nm.
Designing High-Speed Adders in Power-Constrained Environments
Data-driven dynamic logic (D3L) is very efficient when low-power constraints are mandatory. Unfortunately, this advantage is typically obtained at the expense of speed performances. This paper presents a novel technique to realize D3L parallel prefix tree adders without significantly compromising speed performance. When applied to a 64-bit Kogge-Stone adder realized with 90-nm complementary metal-oxide-semiconductor (CMOS) technology, the proposed technique leads to an energydelay product that is 29% and 21% lower than its standard domino logic and conventional D3L counterparts, respectively. It also shows a worst case delay that is 10% lower than that of the D3L approach and only 5% higher than that of the conventional domino logic.
EFFICIENT MULTIOUTPUT CARRY LOOK-AHEAD ADDERS
Addition is the fundamental operation for any VLSI processors or Digital Signal Processing (DSP). In this paper we present an efficient implementation of a 16-bit Manchester carry chain (MCC) adder using an enhanced multiple output domino logic. In adder circuits the main drawback is propagation delay and to overcome this drawback using domino logic. In this paper 4-bit, 8-bit and 16-bit adders are been designed and power, delay and area are measured using TANNER tool, and then compared with the conventional adder. The experimental results reveal that the proposed adders achieve delay, power and area reductions for Multi bit addition.
Design of 64-bit Full Adder by using Dynamic Feedthrough Logic
2012
Full Adder are important component in application such as Digital Signal Processing (DSP) architecture and microprocessor. In addition to its main task , which adding two numbers. This Paper presents the design of high performance low dynamic power arithmetic circuit using a new CMOS Dynamic Feedthrough Logic (DFTL) and Analyzes power and Performance of Them and Compare this to Standard CMOS Logic. This is implemented in .350um Technology. Low power DFTL Arithmetic circuits provide for smaller propagation time Delay, low energy consumption, and similar combined Delay, power consumption when compared with the standard CMOS Logic.
Design of 32Bit Carry-lookahead Adder using Constant Delay Logic
This paper presents an enhanced 32-bit carry lookahead(CLA) adder implementing using the constant delay (CD) logic, targeting at full-custom high-speed applications. The CD characteristic of this logic style regardless of the logic type makes it suitable in implementing complicated logic expressions such as addition. CD logic exhibits a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage is ready. This feature offers performance advantage over static and dynamic domino logic styles in a single-cycle multistage circuit block. Several design considerations including timing window width adjustment and clock distribution are discussed. Using 65-nm general-purpose CMOS technology, the proposed logic demonstrates an average speed up of 94% and 56% over static and dynamic domino logic, respectively, in five different logic gates. Simulation results of 8-bit ripple carry adders show that CD logic is 39% and 23% faster than the static and dynamic-based adders, respectively. CD logic also demonstrates 39% speedup and 64%(22%) energy-delay product (EDP) reduction from static logic at 100% (10%) data activity in 32-bit carry look ahead adders. For 8-bit Wallace tree multiplier, CD logic achieves a similar speedup with at least 50% EDP reduction across all data activities.
Design of a 64-bit low-energy high-performance adder using dynamic feedthrough logic
2009 IEEE International Symposium on Circuits and Systems, 2009
In this work, a new design approach in implementing low-energy, high-performance 64-bit adder using dynamic feedthrough logic (DFTL) is introduced and analyzed. Design issues of using DFTL in several logic depth are analyzed in order to achieve the best optimal balance between performance and power consumption. A "timing window" technique is also proposed to reduce the amount of excessive power dissipation in the DFTL approach. A 64-bit Sklansky carry-merge adder is used as a benchmark comparison between different logic styles including DFTL, CDL, dynamic, and static logic. Simulation results reveal that the proposed work achieves better performance and is more energy efficient than the other logic styles for high performance adder designs.
High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic
Indonesian Journal of Electrical Engineering and Informatics, 2020
Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture have been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 34.53 % improvement in speed, 4.84 % improvement in power consumption and 37.696 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors.