Design of high-speed low-power parallel-prefix adder trees in nanometer technologies (original) (raw)
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Development Of Power And Performance Efficient 32-Bit Variable Latency Parallel Prefix Adder
2020
A variable latency adder pays speculations in arithmetic circuits can replaced with appropriate one, which will produces faster and correct results. In this paper it is proposed Variable-Latency Adder(VLA) based Brent-Kung Parallel-Prefix configuration that outperforms Kogge-Stone. In proposed adder has two stages of operations, one is Pre-processing stage and another one is Generation-stage. The pre-processing stage is the design has propagation and generation circuits. Generation stage producess on the carry generation and result and the performance of the Brent-Kung adder throughout black-cell attain the wide area. Gray cell can be replacing the place of black cell which provide the Efficiency in BKA. Finally, a new move towards the design of efficient 32 bit low-power variable latency parallel prefix Brent Kung Adder (BKA) concentrates the gate levels for improve increase & decreases memory. The Adder which gives the addition process offers great advantages in dropping delay. Br...
Implementation and Estimation of Delay, Power and Area for Parallel Prefix Adders
Parallel Prefix Adders have been established as the most efficient circuits for binary addition. The binary adder is the critical element in most digital circuit designs including digital signal processors and microprocessor data path units. The final carry is generated ahead to the generation of the sum which leads extensive research focused on reduction in circuit complexity and power consumption of the adder. In VLSI implementation, parallel-prefix adders are known to have the best performance. This paper investigates four types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, spanning tree, Brent kung Adder) and compare them to the simple Ripple Carry Adder and Carry Skip Adder. These designs of varied bit-widths are simulated using implemented on a Xilinx version Spartan 3E FPGA. These fast carry-chain carry-tree adders support the bit width up to 256. We report on the area requirements and reduction in circuit complexity for a variety of classical parallel prefix adder structures.
Design and Analysis of 32-bit Parallel Prefix Adders for Low Power VLSI Applications
The basic processes like addition, subtraction can be done using various types of binary adders with dissimilar addition times (delay), area and power consumption in any digital processing applications. To minimize the Power Delay Product (PDP) of Digital Signal Processing (DSP) processors is necessary for high performance in Very Large Scale Integration (VLSI) applications. In this paper, a 32-bit various Parallel Prefix adders design is proposed and compared the performance results on the aspects of area, delay and power. Implementation (Simulation and Synthesis) results really achieve significant improvement in power and power-delay product when compared with the previous bit adders which is used in processors. To reduce the power, here apply the energy recovery logic like power gating technique for all three adders. All the simulations and synthesis results can be noted using Xilinx ISE 14.2i tool.
Design and Estimation of delay, power and area for Parallel prefix adders
In Very Large Scale Integration (VLSI) designs, Parallel prefix adders (PPA) have the better delay performance. This paper investigates four types of PPA's (Kogge Stone Adder (KSA), Spanning Tree Adder (STA), Brent Kung Adder (BKA) and Sparse Kogge Stone Adder (SKA)). Additionally Ripple Carry Adder (RCA), Carry Look ahead Adder (CLA) and Carry Skip Adder (CSA) are also investigated. These adders are implemented in verilog Hardware Description Language (HDL) using Xilinx Integrated Software Environment (ISE) 13.2 Design Suite. These designs are implemented in Xilinx Spartan 6 Field Programmable Gate Arrays (FPGA). Delay and area are measured using XPower analyzer and all these adder's delay, power and area are investigated and compared finally.
Comparative Analysis of Adders Parallel-Prefix Adder for Their Area, Delay and Power Consumption
Parallel Prefix adders have been one of the most notable among more than a few designs proposed in the past. Parallel Prefix adders (PPA) are family of adders derived from the generally known carry look ahead adders. The need for a PPA is that it is mostly fast when compared with Ripple Carry Adders (RCA). The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, and fan-out and interconnect count of logic circuits. In this paper, a comparison of four 8-bit parallel-Prefix adders (Ladner-Fischer Adder (LFA), Kogge-Stone Adder (KSA), Bent-Kang Adder (BKA) and Han-Carlson Adder (HCA)) in their area, delay, power is proposed. In this proposed system Ladner-Fischer adder, Kogge-Stone adder, Bent-Kang adder and Han-Carlson adder, the Parallel Prefix adder are used for comparison. The results reveal that proposed Han-Carlson adder Parallel-Prefix Adder is more competent than other three types of Parallel-Prefix adder in terms of area, delay & power. Simulation results are compared and verified using Xilinx 8.1i software.
Parallel Prefix adders have been one of the most notable among more than a few designs proposed in the past. Parallel Prefix adders (PPA) are family of adders derived from the generally known carry look ahead adders. The need for a Parallel Prefix adder is that it is mostly fast when compared with ripple carry adders. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, and fan-out and interconnect count of logic circuits. In this paper, a comparison of two 8-bit parallel-Prefix adders (Ladner-Fischer adder and Han-Carlson adder) in their area, delay, power is proposed. In this proposed system Ladner-Fischer adder and Han-Carlson adder parallel prefix adder are used for comparison. The results reveal that the proposed Han-Carlson adder Parallel-Prefix Adder is more competent than Ladner-Fischer Parallel-Prefix adder in terms of area, delay & power. Simulation results are compared and verified using Xilinx 8.1i software.
Purpose -Demand and popularity of portable electronic devices are driving the designers to strive for higher speeds, long battery life and more reliable designs. Recently, an overwhelming interest has been seen in the problems of designing digital systems with low power at no performance penalty. Most of the very large-scale integration applications, such as digital signal processing, image processing, video processing and microprocessors, extensively use arithmetic operations. Binary addition is considered as the most crucial part of the arithmetic unit because all other arithmetic operations usually involve addition. Building low-power and high-performance adder cells are of great interest these days, and any modifications made to the full adder would affect the system as a whole. The full adder design has attracted many designer's attention in recent years, and its power reduction is one of the important apprehensions of the designers. This paper presents a 1-bit full adder by using as few as six transistors (6-Ts) per bit in its design. The paper aims to discuss these issues. Design/methodology/approach -The outcome of the proposed adder architectural design is based on micro-architectural specification. This is a textual description, and adder's schematic can accurately predict the performance, power, propagation delay and area of the design. It is designed with a combination of multiplexing control input (MCIT) and Boolean identities. The proposed design features lower operating voltage, higher computing speed and lower energy consumption due to the efficient operation of 6-T adder cell. The design adopts MCIT technique effectively to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. Findings -The proposed adder circuit simulated results are used to verify the correctness and timing of each component. According to the design concepts, the simulated results are compared to the existing adders from the literature, and the significant improvements in the proposed adder are observed. Some of the drawbacks of the existing adder circuits from the literature are as follows: The Shannon theorem-based adder gives voltage swing restoration in sum circuit. Due to this problem, the Shannon circuit consumes high power and operates at low speed. The MUX-14T adder circuit is designed by using multiplexer concept which has a complex node in its design paradigm. The node drivability of input consumes high power to transmit the voltage level. The MCIT-7T adder circuit is designed by using MCIT technique, which consumes more power and leads to high power consumption in the circuit. The MUX-12T adder circuit is designed by MCIT technique. The carry circuit has buffering restoration unit, and its complement leads to high power dissipation and propagation delay. Originality/value -The new 6-T full adder circuit overcomes the drawbacks of the adders from the literature and successfully reduces area, power dissipation and propagation delay.
Simulation and Analysis of different CMOS Full Adders for Delay Optimisation
IJRASET, 2021
Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK-180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay.
High performance microprocessor units require high performance adders and other arithmetic units. Modern microprocessors are however 32-bits or 64-bits as that is the minimum required for floating point arithmetic as per the IEEE 754 Standard. 8-bit and 16-bit arithmetic processors are normally found in micro-controller applications for embedded systems where high speed is important but low power constraints dominate system design. A good metric of performance on such designs would be the power-delay product (or equivalently energy per bit.) Manydesigns give a high speed at the cost of more power or low power at the cost of low speed. The design of a 16-bit Brent Kung adder presented here has the lowest delay (among the adders compared, Table 2) and also the lowest power-delay product (among the adders compared, Table 2) in similar technology nodes. The design makes use of logical effort [1] based sizing of transistors and advanced layout techniques like fingering and inter-digitati...