Roughness Metrology of Gate All Around Silicon Nano Wire Devices (original) (raw)
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Nanotechnology, 2013
This paper presents a non-lithographic approach to generate wafer-scale single crystal silicon nanowires (SiNWs) with controlled sidewall profile and surface morphology. The approach begins with silver (Ag) thin-film thermal dewetting, gold (Au) deposition and lift-off to generate a large-scale Au mesh on Si substrates. This is followed by metal-assisted chemical etching (MacEtch), where the Au mesh serves as a catalyst to produce arrays of smooth Si nanowires with tunable taper up to 13 • . The mean diameter of the thus fabricated SiNWs can be controlled to range from 62 to 300 nm with standard deviations as small as 13.6 nm, and the areal coverage of the wire arrays can be up to 46%. Control of the mean wire diameter is achieved by controlling the pore diameter of the metallic mesh which is, in turn, controlled by adjusting the initial thin-film thickness and deposition rate. To control the wire surface morphology, a post-fabrication roughening step is added to the approach. This step uses Au nanoparticles and slow-rate MacEtch to produce rms surface roughness up to 3.6 nm.
IEEE Transactions on Electron Devices, 2000
We study the effect of surface roughness (SR) at the Si/SiO 2 interfaces on transport properties of quasi 1-D and 2-D silicon nanodevices by comparing the electrical performances of nanowire (NW) and double-gate (DG) field-effect transistors. We address a full-quantum analysis based on the 3-D self-consistent solution of the Poisson-Schrödinger equation within the coupled mode-space nonequilibrium Green function (NEGF) formalism. The influence of SR scattering is also compared with phonon (PH) scattering addressed in the self-consistent Born approximation. We analyze transfer characteristics, current spectra, density of states, and low-field mobility of devices with different lateral size, showing that the dimensionality of the quasi 1-D and 2-D structures induces significant differences only for thin silicon thicknesses. Thin NWs are found more sensitive to the SR-induced variability of the threshold voltage with respect to the DG planar transistors.
Advances in Materials and Processing Technologies, 2019
The defect-free ultra-thin Si wafers with high surface quality have a huge demand in the solar cell-based industry. However, the currently employed wafer slicing methods result in various defects like wafer warpage, variation in thickness, surface and sub-surface cracks, and twin boundaries along with high surface roughness of around 3-5 µm. Therefore, in order to minimise the effect of mechanical machining on the wafer produced, wire-EDM as an alternative method has received attention in the recent past. This work presents the experimentation to understand the effect of wire-EDM on the surface quality and the wafer-thickness variation along the wafer height. The results show that the variation in wafer thickness can be minimised by increasing the parametric values of wire tension, wire feed, and dielectric flushing pressure. These parametric conditions help in better removal of clogged debris in the inter-electrode gap, which in turn improves the slicing process efficiency. The surface roughness values were found to be present in the range of 1 to 2.3 µm. In general, craters due to plasma sparks were visible on the wafer surface while analyzing through SEM micrographs, which also contributes to the surface roughness.
Three-Dimensional Real-Space Simulation of Surface Roughness in Silicon Nanowire FETs
IEEE Transactions on Electron Devices, 2000
We address the transport properties of narrow gateall-around Silicon nanowires in the presence of surface-roughness (SR) scattering at the Si/SiO 2 interface, considering nanowire transistors with a cross section of 3 × 3 nm 2 and gate length of 15 nm. We present transfer characteristics and effective-mobility calculations based on a full 3-D real-space self-consistent Poisson-Schrödinger solver within the nonequilibrium Green's function formalism. The effect of SR is included via a geometrical method consisting in a random realization of potential fluctuations described via an exponential autocorrelation law. The influence on transfer characteristics and on low-field mobility is evaluated by comparison with the clean case and for different values of the root mean square of potential fluctuations. The method allows us to exactly account for mode-mixing and subband fluctuations and to evaluate the effect of SR up to all orders of the interaction. We find that SR scattering is mainly responsible for positive thresholdvoltage shift in the low-field regime, whereas SR-limited mobility slowly depends on the linear charge density, showing the inefficiency of mode-mixing scattering mechanism for very narrow wires.
Journal of Nanoscience and Nanotechnology, 2017
In this paper, characteristics of line edge roughness (LER) and process variation effect (PVE) were investigated for a three stacked gate-all-around (GAA) nanowire (NW) field effect transistor (FET) through 3-D technology computer-aided design (TCAD) simulations. The stacked device has robust immunity for GAA LER as well as high driving current in comparison with single NW FET. On the other hand, the stacked device has PVE, which causes the difference of channel thickness on each stack. Particularly, the channel of the bottom region has larger channel radius than that of the other stacks. As the disparity of each stack becomes larger, the driving currents are concentrated on the bottom channel, which leads to high stress such as hot carrier degradation on the bottom channel.
A Simple Method for Measuring Si-Fin Sidewall Roughness by AFM
IEEE Transactions on Nanotechnology, 2009
The gate oxide reliability and the electrical behavior of FinFETs are directly related to the surface characteristics of the fin vertical sidewalls. The surface roughness of the fin sidewalls is one of the most important structural parameters to be monitored in order to optimize the fin patterning and postetch treatments. Because of the nanometer-scale dimensions of the fins and the vertical orientation of the sidewall surface, their roughness measurement is a serious challenge. In this paper, we describe a simple and effective method for measuring the sidewall morphology of silicon fins by conventional atomic force microscopy. The present methodology has been employed to analyze fins as etched by reactive ion etching and fins repaired by sacrificial oxidation. The results show that sacrificial oxidation not only reduces the roughness of the sidewalls, but also rounds the top corners of silicon fins. The present method can also be applied to characterize sidewall roughness of other nanostructures and materials such as the polysilicon gate of transistors or nanoelectromechanical beams. Index Terms-Atomic force microscopy (AFM), FinFET, roughness of silicon fin sidewall, sacrificial oxidation. I. INTRODUCTION F INFET [1], a nonplanar double-gate transistor usually built on a silicon-on-insulator (SOI) substrate, is a promising candidate for CMOS scaling down to the 10-nm regime. In previous years, several electrical characterizations of FinFET [2] have demonstrated its effective control of short-channel effects [3], higher current drive, and scalability [4]. The CMOS compatibility of its fabrication process flow explains the growing interest of the microelectronics industry for the advanced MOS architecture.
Determination of optimal parameters for CD-SEM measurement of line-edge roughness
Proc. SPIE, 2004
The measurement of line-edge roughness (LER) has recently become a topic of concern in the litho-metrology community and the semiconductor industry as a whole. The Advanced Metrology Advisory Group (AMAG), a council composed of the chief metrologists from the International SEMATECH (ISMT) consortium's Member Companies and from the National Institute of Standards and Technology (NIST), has a project to investigate LER metrics and to direct the critical dimension scanning electron microscope (CD-SEM) supplier community towards a semiconductor industrybacked, standardized solution for implementation. The 2003 International Technology Roadmap for Semiconductors (ITRS) has included a new definition for roughness. The ITRS envisions root mean square measurements of edge and width roughness. There are other possible metrics, some of which are surveyed here. The ITRS envisions the root mean square measurements restricted to roughness wavelengths falling within a specified process-relevant range and with measurement repeatability better than a specified tolerance. This study addresses the measurement choices required to meet those specifications. An expression for the length of line that must be measured and the spacing of measurement positions along that length is derived. Noise in the image is shown to produce roughness measurement errors that have both random and nonrandom (i.e., bias) components. Measurements are reported on both UV resist and polycrystalline silicon in special test patterns with roughness typical for those materials. These measurements indicate that the sensitivity of a roughness measurement to noise depends importantly both on the choice of edge detection algorithm and the quality of the focus. Measurements are less sensitive to noise when a model-based or sigmoidal fit algorithm is used and when the images are in good focus. Using the measured roughness characteristics for UV resist lines and applying the ITRS requirements for the 90 nm technology node, the derived expression for sampling length and sampling interval implies that a length of line at least 8 times the node (i.e., 720 nm) must be measured at intervals of 7.5 nm or less.
2016
Nanowire based devices are becoming more promising, because size scaling in CMOS technology continues to follow Moore‘s Law and hence device scaling based on the planar structures becomes difficult and is about to reach the end of the technology road map. Another factor is that, as the gate length shortens, the gate control over the channel degrades due to short channel effect and therefore, nanowire based devices were developed as an alternative to ultra-scaled CMOS devices. In this paper the results of measured and analysed electrical data for silicon nanowire will be presented. Two and four probe techniques of measuring electrical data for silicon nanowire were adopted while performing measurements. The paper will also present a review on the synthesis processes of silicon nanowire. Keywords—Semiconductor parameter analyser, CMOS technology, Moore‘s Law, probing techniques, silicon nanowire.
Journal of Applied Physics, 2012
With the constant decrease of semiconductor device dimensions, line width roughness (LWR) becomes one of the most important sources of device variability and thus needs to be controlled below 2 nm for the future technological nodes of the semiconductor roadmap. The LWR control at the nanometer scale requires accurate measurements, which are inevitably impacted by the noise level of the equipment that causes bias from true LWR values. In this article, we compare the capability of two metrology tools, the critical dimension scanning electron microscopy (CD-SEM) and critical dimension atomic force microscopy (CD-AFM) to measure the true line width roughness of silicon and photoresist lines. For this purpose, we propose several methods based on previous works to estimate the noise level of those two equipments and thus extract the true LWR. One of the developed methods for the CD-SEM technique generalizes the power spectral densities (PSD) fitting method proposed by Hiraiwa and Nishida with a more universal autocorrelation function, which includes both correlation length and roughness exponent. However, PSD fitting method could not be used with CD-AFM due to the time consuming character of this technique. Hence, other experimental protocols have been set up for CD-AFM in order to accurately characterize the LWR. Our study shows that the CD-SEM technique combined with our PSD fitting method is much more powerful than CD-AFM to get all roughness information (true LWR, correlation length, and roughness exponent) with a good accuracy and efficiency on hard materials such as silicon. Concerning materials degradable under electron beam exposure such as photoresist, the choice is more disputable, since ultimately they are impacted by the electrons. Fortunately, our PSD fitting method allows working with low number of integration frames, which limits the resist degradation. Besides, we have highlighted some limitations of the CD-AFM technique due to the tip diameter. This technique can underestimate LWR if the roughness presents significant amount of high frequency components, as it is the case for photoresist patterns. So far, there is no universal technique to accurately estimate the LWR on any materials. Nevertheless, the CD-SEM protocol we propose opens a way for a better characterization of the photoresist LWR after lithography and a better understanding of the LWR transfer during the plasma etching steps involved in gate patterning processes. V
Spatial Sensitivity of Silicon GAA Nanowire FETs under Line Edge Roughness Variations
IEEE Journal of the Electron Devices Society, 2018
Standard analysis of variability sources in nanodevices lacks information about the spatial influence of the variability. However this spatial information is paramount for the industry and academia to improve the design of variabilityresistant architectures. A recently developed technique, the Fluctuation Sensitivity Map (FSM) is used to analyse the spatial effect of the Line Edge Roughness (LER) variability in key figures-ofmerit (FoM) in silicon Gate-All-Around (GAA) nanowire (NW) FETs. This technique gives insight about the local sensitivity identifying the regions inducing the strongest variability into the FoM. We analyse both 22 nm and 10 nm gate length GAA NW FETs affected by the LER with different amplitudes (0.6, 0.7, 0.85 nm) and correlation lengths (10, 20 nm) using in-house 3D quantum-corrected drift-diffusion simulation tool calibrated against experimental or Monte Carlo data. The FSM finds that the gate is the most sensitive region to LER deformations. We demonstrate that the specific location of the deformation inside the gate plays an important role in the performance and that the effect of the location is also dependent on the FoM analysed. Moreover, there is a negligible impact on the device performance if the LER deformation occurs in the source or drain region.