Low-frequency noise and mobility in triple-gate silicon-on-insulator transistors: Evidence for volume inversion effects (original) (raw)
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1/f noise in advanced CMOS transistors
IEEE Instrumentation & Measurement Magazine, 2000
C omplementary metal-oxide-semiconductor (CMOS) technology is dominant in the microelectronics industry for a wide range of applications, including analog, digital, RF, and sensor systems. The advantages of silicon CMOS technology compared to bipolar technology as well as transistors in other semiconductors is well-established. CMOS technology scaling has been a main drive for continuous progress in the silicon based semiconductor industry over the past two decades . The continuous downscaling of CMOS technologies towards nano feature size has increased the performance of integrated circuits considerably. However, one important limitation of MOSFET downscaling is an increase of 1/f noise (often referred to as low-frequency noise), since the 1/f noise increases as the reciprocal of the device area [2], . Furthermore, the development of nano-sized CMOS technologies has led to the observation of random telegraph signals (RTS) yielding large low frequency current fluctuations. Excessive low-frequency noise introduces serious limitations on the functionality of analog and digital circuits since it deteriorates the noise figure of operational amplifiers and A/D and D/A converters. Lowfrequency noise diminishes the signal-to-noise-ratio (SNR) of CMOS sensors, such as IR or CMOS image sensors [5] .
Low-Frequency Noise in MOSFETs
—As soon as inherent noise of MOSFET becomes an issue in the design of ICs, accurate physics-based models are necessary. The present paper reviews the different noise sources responsible for MOSFET drain current fluctuation. The long-running question of the physical origin of 1/f noise is briefly addressed. Special attention is paid to the Random Telegraph Noise (RTN) since it gets as significant as statistical variability in deeply-scaled CMOS technologies. Due to the extreme complexity of the underlying physical mechanism, which is capture and emission of carrier by an oxide defect, we adopt a phenomenological approach. A stochastic model is firstly derived. Then, the fundamental physical parameters are discussed based on the simple Shockley-Read-Hall theory and the charge sheet approximation.
Charge-Based Compact Model for Bias-Dependent Variability of 1/ fff Noise in MOSFETs
IEEE Transactions on Electron Devices, 2016
Variability of low frequency noise (LFN) in MOSFETs is bias-dependent. Moderate-to large-sized transistors commonly used in analog/RF applications show 1/f-like noise spectra, resulting from the superposition of random telegraph noise (RTN). Carrier number and mobility fluctuations are considered as the main causes of low frequency noise. While their effect on the bias-dependence of LFN has been well investigated, the way these noise mechanisms contribute to the bias-dependence of variability of LFN has been less well understood. LFN variability has been shown to be maximized in weak inversion (sub-threshold), while increased drain bias also increases LFN variability. However, no compact model has been proposed to explain this bias-dependence in detail. In combination with the charge-based formulation of LFN, the present paper proposes a new model for bias-dependence of LFN variability. Comparison with experimental data from moderately-sized NMOS and PMOS transistors at all bias conditions provides insight into how carrier number and mobility fluctuation mechanisms impact the bias-dependence of LFN variability.
2015 International Conference on Noise and Fluctuations (ICNF), 2015
In this paper, a thorough statistical investigation of low frequency noise (LFN) variability in MOSFETs is presented. In smaller-sized devices, noise fluctuations are areadominated. In moderate-to large-sized transistors (Area >> 1μm 2 ), normalized noise fluctuations are roughly independent of area, but show a distinct degradation towards weak inversion (subthreshold). A new model is proposed for the gatevoltage dependence of 1/f noise variations in moderately-sized transistors. We show that the gate-voltage dependence may be related to transconductance-to-current ratio g m /I D . Extensive measurements of low frequency noise variability in experimental 180nm CMOS confirm the newly proposed model.
Improved analysis and modeling of low-frequency noise in nanoscale MOSFETs
Solid-State Electronics, 2012
Extensive investigation of the low-frequency noise in n-channel and p-channel MOSFETs, with high-k gate stack and channel length varying from 1.8 lm down to 26.4 nm, has been carried out. The results demonstrate that the carrier number fluctuation with correlated mobility fluctuations describes accurately and continuously the 1/f noise for all operation regions, i.e. from weak to strong inversion and from linear to saturation. It has been found that the product of the Coulomb scattering coefficient and the effective carrier mobility a sc l eff is constant over a wide range of the drain current due to the interplay of the Coulomb scattering coefficient a sc and the effective carrier mobility l eff variations. In addition, a non-linear increase in the square root of the input gate voltage noise with the gate voltage overdrive was observed explained by the surface roughness scattering. The overall results lead to an analytical expression for the 1/f noise model, enabling to predict the noise level of a transistor with any channel dimensions using its transfer characteristic. This finding makes the noise model suitable for circuit simulation tools.
IEEE Transactions on Electron Devices, 2010
This paper presents a study on 1/f noise in MOSFETs under large-signal (LS) operation, which is important in CMOS analog and RF integrated circuits. The flicker noise is modeled with noise sources as a perturbation in the semiconductor equations employing McWhorter's oxide-trapping model and Hooge's empirical 1/f noise model. Numerical results are shown for 1/f noise in the MOSFET in both small-signal operation and periodic LS operation. It is shown that McWhorter's model does not give any significant 1/f noise reduction when the oxide traps are distributed uniformly in energy and space. In contrast, Hooge's model gives almost 6-dB 1/f noise reduction as the gate OFF-voltage decreases below the threshold voltage. It is found that both models fall short of explaining the noise reduction by more than 6 dB, as observed experimentally in the literature. However, when only one active oxide trap is considered, which generates random telegraph signal (RTS) in drain current, the LS operation gives more than 6-dB low-frequency RTS noise reduction. Index Terms-Cyclostationary noise, Hooge's empirical 1/f noise model, McWhorter's oxide-trapping model, 1/f noise in MOSFETs. I. INTRODUCTION F OR the analysis and design of CMOS analog and RF integrated circuits, 1/f noise in MOSFETs is one of the factors limiting the achievable dynamic range of electronic MOS circuits. For example, 1/f noise has been known as the major cause of close-in phase noise in CMOS RF oscillators [1]. The analysis and characterization of 1/f noise in MOSFETs is typically performed for MOSFETs in the small-signal operation, where only dc biases are imposed on the device electrodes.
IEEE Transactions on Electron Devices, 1995
The empirical relationship between the device transconductance and the input-referred noise spectral density observed on partially depleted SOI n-MOSFETs is examined for other types of devices. As is shown, buried-channel p-MOSFETs processed in the same 1 μm CMOS SOI technology show the same behavior. The exponential dependence is also observed for SDI n-MOSFETs fabricated in a 3 μm CMOS technology, strongly emphasizing the generality of the result. Furthermore, it is valid both in linear operation (weak and strong inversion) and in saturation. The physical back-ground of this correlation is further elaborated and a new relationship is derived for the noise in the subthreshold regime.
Solid-State Electronics, 2005
The drain current activation energy dependence on the gate voltage is first evaluated from temperature measurements in both low temperature (6600°C) polysilicon thin film transistors and in crystalline silicon N-MOSFETs, operating from sub-threshold to above-threshold regions. The noise behaviour of these transistors is then described with a low frequency noise model based on the Meyer-Neldel drain current expression. This model is built on carrier fluctuations at the gate oxide/active layer interface and the corresponding defect density is then deduced. It suggests that these defects close to the interface, causing detrapping/trapping processes of carriers and fluctuations of the flat-band voltage, are mainly responsible for the low frequency noise in the two operating modes. Noise measurements on different N-MOS transistors are confronted to result from the presented model.
Origin of the low-frequency noise in n-channel FinFETs
Solid-State Electronics, 2013
The origin of the low-frequency noise is investigated in n-channel fin-shaped field-effect transistors (Fin-FETs) in terms of the channel length and fin width. In long-channel and wide fin devices, the spectra are dominated by 1/f noise due to carrier number fluctuation, correlated with mobility fluctuations. In longchannel and narrow fin devices, the spectra are composed of both 1/f and excess generation-recombination (g-r) noise components. Analysis of the g-r noise parameters lead to the conclusion that the g-r noise originates from traps in the sidewall gate oxides and in a depletion region near the sidewall interfaces. In short-channel devices, the spectra show 1/f behavior in the weak inversion described by carrier number fluctuations and g-r noise component in the low drain current region, possibly originating from the source and drain contacts process.
Modeling the gate current 1/f noise and its application to advanced CMOS devices
9th International Conference on Solid-State and Integrated-Circuit Technology , 2008
In this work we propose an analytical model for the gate current Ilf noise in CMOS devices. The model is based on a simple idea: one electron trapped in the dielectric switches-off the tunneling through the oxide over an effective blocking area. The model allows evaluating the effective trap density inside the gate dielectric as a function of energy from measurements of the gate current Ilf noise versus gate voltage. Experimental data on advanced CMOS devices confirm the validity and the usefulness of the proposed model.