Microcode Generation for flexible parallel target architectures (original) (raw)

Microcode generation for flexible parallel architectures

Proceedings of the IFIP WG10, 1994

Abstract: Advanced architectural features of microprocessors like instruction level parallelism and pipelined functional hardware units require code generation techniques beyond the scope of traditional compilers. Additionally, recent design styles in the area of ...

Automated Synthesis of Instruction Codes in the Context of Micro-architecture Design

2010 10th International Conference on Application of Concurrency to System Design, 2010

ABSTRACT There is a critical need for design automation in micro architectural modelling and synthesis. One of the areas which lacks the necessary automation support is synthesis of instruction codes targeting various design optimality criteria. This paper aims to fill this gap by providing a formal method and software tool for synthesis of instruction codes given the description of a processor as a set of instructions. The method is based on the Conditional Partial Order Graph (CPOG) model introduced recently, which is a formalism for efficient specification and synthesis of microcontrol circuits. It describes a system as a functional composition of its behavioural scenarios, or instructions, each of them being a partial order of events. In order to distinguish instructions within a CPOG they are given different encodings represented with Boolean vectors. Size and latency of the final microcontroller significantly depends on the chosen encodings, thus efficient synthesis of instruction codes is essential. This paper presents a method for optimal encoding of a given set of partial orders so that a CPOG containing all of them has the minimum complexity, thereby leading to the smallest and fastest controller.