A new configurable and scalable architecture for rapid prototyping of asynchronous designs for signal processing (original) (raw)

Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454), 2000

Abstract

In this paper we present the architecture and implementation of our new configurable and scalable chip well suited for rapid prototyping of asynchronous designs. A flexible number of arithmetic operators, e.g. 720 add/sub operators for the first chip, are interconnected via a configurable network. For demonstration a DCT algorithm was mapped onto the chip

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