A Dual-Band CMOS Voltage-Controlled Oscillator Implemented With Dual-Resonance LC Tank (original) (raw)
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Dual-band CMOS voltage-controlled oscillator with comparable outpower at both bands
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In this paper, a 2.4 GHz fully integrated LC voltage controlled oscillator (VCO) for RF wireless applications is presented. The VCO circuit is designed using TSMC 130 nm CMOS process. The circuit design is based on differential oscillator structure with cross-coupled NMOS transistors which achieves low power dissipation and low phase noise. Simulation and layout of the VCO is carried out using ADS Tool. The VCO operates from a supply voltage of 1.8 V and consumes 19.62 mW of power. After simulating the proposed design the VCO shows a phase noise of-128.68 dBc/Hz at 1 MHz offset frequency from a 2.4 GHz carrier signal. The frequency range of the VCO is from 2.36 GHz to 2.61 GHz when the control voltage changes from 0 to 2 V. The FOM is obtained as-183.73 dBc/Hz. The total chip area, including pads, occupies 0.7 mm × 0.7 mm.
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2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT), 2013
This letter presents a low phase noise BiCMOS dual-band voltage-controlled oscillator (VCO). The designed circuit consists of a dual-resonance LC resonator and a Colpitts negative resistance cell. The dual-resonance LC resonator comprises a series-tuned LC resonator and a parallel resonant resonator. The proposed VCO has been implemented with the TSMC 0.18 μm SiGe 3P6M BiCMOS process. The VCO can generate differential signals in the frequency range of 3.91~4.17 GHz and 7.24~7.80GHz with core power consumption is 6.30mW and 5.88mW at the dc bias of 1.4 V respectively. At 4.0 GHz and 7.74 GHz, phase noise at 1MHz offset is -121.13dBc/Hz and -115.87dBc/GHz respectively. The die area of the dual-band VCO is 0.485×0.800 mm 2 .
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A low phase noise CMOS complementary cross-coupled LC-tank voltage-controlled oscillator (VCO), implemented with TSMC 0.18 µm 1P6M CMOS technology, is presented. Double pair pseudoresistance transistors biased by the tapped center of the inductor are utilized to reduce the DC bias current. The circuit consumes 1.55 mA from a 1.5 V supply voltage which saves up to 52.4% power, compared with the conventional one. Furthermore, an adaptive body biasing technique (ABB) is used to overcome the effect of PVT variations. The VCO is tunable from 2.58 to 3.07 GHz and has a phase noise −122.7 dBc/Hz at 1 MHz offset from the 3 GHz carrier. The Figure of Merit (FOM) of the proposed VCO is −188.8 dBc, and the figure of merit including the tuning range (FOM T ) is −193.5 dBc.
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