Extended time handling strategies for the improvement of prediction accuracy in event driven power estimation (original) (raw)
Related papers
Power modeling for high-level power estimation
Very Large Scale Integration (VLSI) …, 2000
In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching statistics. The resulting power macromodel, consisting of a single four-dimensional table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gate-level) description of the circuit, we describe a characterization process by which such a table model can be automatically built. The four dimensions of our table-based model are the average input signal probability, average input transition density, average spatial correlation coefficient and average output zero-delay transition density. This approach has been implemented and models have been built for many benchmark circuits. Over a wide range of input signal statistics, we show that this model gives very good accuracy, with an RMS error of about 4% and average error of about 6%. Except for one out of about 10,000 cases, the largest error observed was under 20%. If one ignores the glitching activity, then the RMS error becomes under 1%, the average error becomes under 5% and the largest error observed in all cases is under 18%.
1999
This paper presents a efficient approach for the estimation of signal activity figures based on a gate level description of a digital circuit. Exploiting an event oriented simulation system a methodology for calculating very accurate power estimates for digital circuits is presented. A calibration scheme for characterizing the power dissipation of logic gates based on a few key parameters will be outlined. The proposed method proves that the use of an event oriented simulation system calibrated with these gate specific parameters allows power estimations which are comparable to transistor level (SPICE) simulation accuracy. This is essential for the analysis of large circuits, because the proposed event driven simulation system is about 10000 times faster than transistor level simul ation. Experimental results and benchmarks are presented which demonstrates significant improvements in terms of performance, accuracy and flexibility of this approach compared to other state of the art power estimation met hods.
This paper presents a efficient approach for the estimation of signal activity figures based on a gate level description of a digital circuit. Exploiting an event oriented simulation system a methodology for calculating very accurate power estimates for digital circuits is presented. A calibration scheme for characterizing the power dissipation of logic gates based on a few key parameters will be outlined. The proposed method proves that the use of an event oriented simulation system calibrated with these gate specific parameters allows power estimations which are comparable to transistor level (SPICE) simulation accuracy. This is essential for the analysis of large circuits, because the proposed event driven simulation system is about 10000 times faster than transistor level simul ation. Experimental results and benchmarks are presented which demonstrates significant improvements in terms of performance, accuracy and flexibility of this approach compared to other state of the art power estimation met hods.
Power Macromodeling For High Level Power Estimation
Proceedings of the 34th Design Automation Conference, 1997
A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching activity. The resulting power macromodel, consisting of a single three dimensional table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gatelevel) description of the circuit, we describe a characterization process by which such a table model can be automatically built. In contrast to other proposed techniques, this can be done for any given logic circuit without any user intervention, and applies to all possible input/output signal statistics; it does not require one to construct specialized analytical equations for the power dissipation. The three dimensions of our table-based model are the average input signal probability, average input transition density, and average output zero-delay transition density. This approach has been implemented and models have been built for many benchmark circuits. Over a wide range of input signal statistics, we show that this model gives very good accuracy, with an RMS error of under about 6%.
IJERT-Design and Implementation of Power Estimation Technique for Digital Circuits
International Journal of Engineering Research and Technology (IJERT), 2014
https://www.ijert.org/design-and-implementation-of-power-estimation-technique-for-digital-circuits https://www.ijert.org/research/design-and-implementation-of-power-estimation-technique-for-digital-circuits-IJERTV3IS041503.pdf Nowadays modelling and estimation of power dissipation in the early stages of VLSI design flow has become more important since the intensive scaling of transistors results in higher leakage currents. Various highly advanced Electronic Design Automation (EDA) tools have emerged in recent years to address the issue of power consumption. With a vast number of these power measurement tools emerging, analyzing power consumed by digital circuits has not only become easier but also more effective methods are deployed to optimize digital circuits to dissipate less power. This paper describes the technique of estimating the dynamic as well as the static power consumed by the digital circuit. This technique uses various design constraint files as its input such as gate-level netlist, library file, VCD file and produces the power report. This method uses "gpdk 180nm" library file for estimating the power. This process of power estimation is implemented using combination of C++ and PERL coding languages. To calculate the power RTL coding is done in Verilog using CADENCE NC-Launch and CADENCE RTL compiler is used to generate the "Gate-Level Netlist". For various standard digital benchmark circuits the power report produced by this technique is tested and compared with the power report generated by CADENCE RC-Compiler.
Analytical Macro-Modeling for High-Level Power Estimation
In this paper, we present a new analytical macro-modeling technique for high-level power estimation. Our technique is based on a parameterizable analytical model that relies exclusively on statistical information of the circuit's primary inputs. During estimation, the statistics of the required metrics are extracted from the input stream and a power estimate is obtained by evaluating a model function that has been characterized in advance. Thus, our model yields power estimates within seconds, since it does not rely on the statistics of the circuit's primary outputs and, consequently, does not perform any simulation during estimation. Moreover, our model achieves significantly better accuracy than previous macro-modeling approaches, because it takes into account both spatial and temporal correlations in the input stream.
PowerSC: A SystemC-based framework for power estimation
2007
Although SystemC is considered the most promising language for system-on-chip functional modeling, it doesn't come with power modeling capabilities. This work presents PowerSC, a novel power estimation framework which instruments SystemC for power characterization, modeling and estimation. Since it is entirely based on SystemC, PowerSC allows consistent power modeling from the highest to the lowest abstraction level. Besides, the framework's API provides facilities to integrate alternative modeling techniques, either at the same or at different abstraction levels. As a result, the required power evaluation infrastructure is reduced to a minimum: the standard SystemC library, the PowerSC library itself and a C++ compiler. Although RTL power macromodeling is a mature research topic, it is not yet broadly accepted in the industrial environment. One of the main reasons impairing its widespread use as a power estimation paradigm is that each macromodeling technique makes some assumptions that lead to some sort of intrinsic limitation, thereby affecting its accuracy. Therefore, alternative macromodeling methods can be envisaged as part of a power modeling toolkit from which the most suitable method for a given component should be automatically selected. This paper describes a new multi-model power estimation engine that selects the macromodeling technique leading to the least estimation error for a given system component depending on its input-vector stream properties. A proper selection function is built after component characterization and used during estimation. Experimental results show that our multi-model engine improves the robustness of power analysis, reducing significantly the average and the maximum estimation errors, as compared to conventional single-model estimation.
Gate-level power estimation using tagged probabilistic simulation
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1998
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a CMOS circuit under a general delay model. This technique is based on the notion of a tagged (probability) waveform, which models the set of all possible events at the output of each circuit node. Tagged waveforms are obtained by partitioning the logic waveform space of a circuit node according to the initial and final values of each logic waveform and compacting all logic waveforms in each partition by a single tagged waveform. To improve the efficiency of tagged probabilistic simulation, only tagged waveforms at the circuit inputs are exactly computed. The tagged waveforms of the remaining nodes are computed using a compositional scheme that propagates the tagged waveforms from circuit inputs to circuit outputs. We obtain significant speed up over explicit simulation methods with an average error of only 6%. This also represents a factor of 2-32 improvement in accuracy of power estimates over previous probabilistic simulation approaches.