A novel ternary more, less and equality circuit using recharged semi-floating gate devices (original) (raw)
Related papers
A Balanced Ternary Multiplication Circuit Using Recharged Semi-Floating Gate Devices
2006 NORCHIP, 2006
This paper presents a multiplier circuit using Balanced Ternary (BT) Notation. The multiplier can multiply both negative and positive numbers, which is one of the advantage able properties of the balanced ternary numbering systems. By using balanced ternary notation, it is possible to take advantage of carry free multiplication, which is exploited in designing a fast multiplier circuit. The circuit is implemented with Recharged Semi-Floating Gate (RSFG) devices. The circuit operates at 1 GHz clock frequency at a supply voltage of only 1.0 Volt. The circuit is simulated by using Cadence R Analog Design Environment, with CMOS090 process parameters, a 90nm General Purpose Bulk CMOS Process from STMicroelectronics with 7 metal layers.
A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices
Proceedings of The International Symposium on Multiple-Valued Logic
This paper presents a novel voltage mode Balanced Ternary Adder (BTA), implemented with Recharged Semi- Floating Gate Devices. By using balanced ternary notation, it possible to take advantage of carry free addition, which is exploited in designing a fast adder cell. The circuit operates at 1 GHz clock frequency. The supply voltage is only 1.0 Volt. The circuit is simulated by using Cadence R Analog Design Environment, with CMOS090 process parameters, a 90nm General Purpose Bulk CMOS Process from STMicroelectronics with 7 metal layers. All the capacitors are metal plate capacitors, based on vertical coupling capacitance between stacked metal plates.
International Journal of High Performance Systems Architecture, 2015
Ternary minimum (AND) and maximum (OR) functions are implemented in this paper based on dynamic logic style, where the clock signal evaluates combinational circuits periodically. Unlike previously presented designs, additional voltage sources are not required in the proposed structures. Transistors divide voltage to achieve standard ternary functions. An initial design is modified gradually to reach a high-performance design with reduced transistor-count and decreased switching activity. New circuits are simulated with carbon nanotube field effect transistor technology in different situations. Simulation results show that the proposed cells are suitable for low-power and high-frequency applications.
Design of Low Power Low Voltage Circuit using CMOS Ternary Logic
— Binary logic and devices have been in use since inception with advancement and technology and millennium gate design era. Now binary logic has become tedious and complicated. For this purpose the low power and low voltage arithmetic and logic circuit designed. In this paper we will presents the design and performance of Arithmetic and Logic circuit using Ternary logic and CMOS design styles. The design is targeted for the 45nm CMOS technology. Design tool for simulation will be MICROWIND 3.1 software and DSCH tool. We will estimate area, power and delay and the design of arithmetic circuit with optimized number of transistors as compared to binary circuit.
A Novel Ternary Switching Element Using CMOS Recharge Semi Floating-Gate Devices
35th International Symposium on Multiple-Valued Logic (ISMVL'05), 2005
In this paper we present a novel voltage mode noninverting CMOS Semi Floating-Gate(SFG) Ternary Switching Element. The design is applicable for reconstructing or refreshing ternary logic signals. The switching points are tuned using capacitive division. A preliminary simulation results from Cadence Spectre with AMS 0.35µmprocess parameters c35b4 is included.
A Novel Ternary Switching Element Using CMOS Recharged Semi-Floating Gate Devices
2005
In this paper we present a novel voltage mode noninverting CMOS Semi Floating-Gate(SFG) Ternary Switching Element. The design is applicable for reconstructing or refreshing ternary logic signals. The switching points are tuned using capacitive division. A preliminary simulation results from Cadence Spectre with AMS 0.35µmprocess parameters c35b4 is included.
Implementation of Ternary Circuits with-Binary Integrated Circuits
IEEE Transactions on Computers, 1977
A general method for implementing ternary circuits with binary integrated circuits is described. The conditions are given for a particular technology to be able to implement ternary circuits. For TTL, COSMOS, and ECL technologies, the necessary circuits are developed. Formulas are provided to obtain the minimum circuit according to the particular function required. Simplification rules corresponding to each technology are given. Some examples illustrate the method. Some dynamical characteristics are shown. Extensions of these results to other technologies and to n-valued circuits are possible. Index Terms-Circuit realization of multivalued functions, combinational circuits, COSMOS integrated circuits, ECL integrated circuits, fundamental ternary circuits, multivalued circuits, ternary logic implementation, TTL integrated circuits.
A proposal for the implementation of ternary digital circuits
Microelectronics Journal, 1997
A nonclassical multi-valued logic based on Post algebra is presented. Besides the conventional Post's cyclic negation, this nonclassical logic algebra defines new operators that simplify the truth-table minimization techniques. An electronic implementation of this algebra for a 3-level logic is proposed. Electronics gates of Post negation and the new operators were designed and simulated using current mode circuits. These gates can be easily interconnected to form flip-flops, counters and other conventional digital gates in a true 3-level gate logic. ASICs with mixed analog/digital high-speed processing can benefit from this current processing ternary logic, which can be easily implemented in bipolar technology.