RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers for SoC applications (original) (raw)

2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2013

Abstract

ABSTRACT We present for the first time the RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers. These wafers are fully compatible with the thermal budget of CMOS process. The investigated SOI wafers with a fixed BOX of 400 nm-thick show effective resistivity values higher than 4 kΩ-cm and harmonic distortion levels lower than -81 dBm for a 900 MHz input signal with +15 dBm, i.e. more than 95 dBc. Our investigations confirm the capability of trap-rich HR-SOI wafer for the integration of RF systems in Si.

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