4 -Rate Linear Phase Detector (original) (raw)

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

This paper presents a 5-Gb/s dual-loop clock and data recovery (CDR) circuit with a compact quarter-rate linear phase detector (PD). The proposed PD not only reduces the complexity of the circuit structure but also employs an UP pulse-widening technique to circumvent the problem of existing narrow UP pulses. Meanwhile, it has the least number of output signals among all the other linear PDs with UP pulse-widening technique. It also provides a data recovery circuit to de-multiplex the input data with no systematic phase offset. An unbalanced charge pump (CP) is also proposed to compensate the unbalanced pulse-width of UP and DN pulses as well as the unequal number of signal between UP and DN pulses. A detailed propagation delay analysis and a set of equations to predict the characteristic curve of the proposed PD is given. In addition, a lock detector with hysteresis property is implemented to ensure proper switching of the loops. Fabricated in 0.18-CMOS technology, the circuit shows that the peak-to-peak jitter of the recovered clock is 30.4-ps and it consumes 71.9-mW from a 1.8 V supply.

A multi-phase 10 GHz VCO in CMOS/SOI for 40 Gbits/s SONET OC-768 clock and data recovery circuits

RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE Radio Frequency integrated Circuits, 2005

This paper presents the design of a multi-phase voltage-controlled oscillator (VCO) in CMOS/SOI technology, based on a ring amplifier with LC resonators. This circuit is a key block of a 40 Gbit/s serial communications system. Operating at a speed of one-fourth of the nominal data rate, this CMOS architecture complies with SONET OC-768 standard. The circuit exhibits a 25% frequency

A CMOS clock recovery circuit for 2.5-Gb/s NRZ data

Solid-State Circuits, IEEE Journal of, 2001

This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-m digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 2 7 1 and a phase noise of 80 dBc/Hz at a 5-MHz offset. The core circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8 0.4 mm 2 .

A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector

IEICE Transactions on Electronics, 2006

A clock and data recovery (CDR) circuit using a new halfrate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Return-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-µm N-well CMOS technique. Experimental results demonstrate that it can achieve the peak-to-peak jitter of the recovered clock and the retimed data about 120 ps and 170 ps, respectively, while operating at the input data rate of 1 Gb/s. The total power dissipation of the CDR is 64.8 mW for the supply 3 V.

A fully integrated SONET OC48 transceiver in standard CMOS

IEEE Journal of Solid-state Circuits, 2001

This paper presents the first fully integrated, SONET OC-48 (2.488/2.666 Gb/s) transceiver using a standard CMOS process. Careful design methodology combined with a standard CMOS technology allows performance exceeding SONET requirements with the added benefits of reduced power dissipation, higher integration levels, and simplified manufacturability as compared to other fabrication technologies. This chip, designed using a standard 0.18-m CMOS technology, has a total power dissipation of 500 mW and an rms jitter of 1 ps.

A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit

IEEE Journal of Solid-state Circuits, 2006

A 200-Mbps 2-Gbps continuous-rate clock-anddata-recovery (CDR) circuit using half-rate clocking is presented. To detect the data with wide-range bit rates, a frequency tracing circuit (FTC) is used to aid the frequency acquisition. A wide-range and low gain voltage-controlled oscillator (VCO) is also presented by using analog and digital controlled mechanisms. A two-level bang-bang phase detector is utilized to improve the jitter performance and speed up the locking process. This CDR circuit has been realized in a 2P4M 0.35-m CMOS process. The experimental results show that this CDR circuit with the proposed FTC can receive 2 31 1 pseudorandom bit stream when the bit rate ranges from 200 Mbps to 2 Gbps without the harmonic-locking issue. All measured bit error rates are below 10 12 . The measured root-mean-square and peak-to-peak jitters are 5.86 ps and 41.8 ps, respectively, at 2 Gbps.

A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition

IEEE Journal of Solid-State Circuits, 2006

A 0.25-m CMOS, multi-rate clock and data recovery (CDR) circuit that leverages unique analog/digital boundaries in its phase detector and loop filter to achieve a fully integrated CDR implementation with excellent performance, compact area, and low power dissipation is presented. Key circuit blocks include a phase-to-digital converter that combines a Hogge detector with a continuous-time first-order Sigma-Delta analog-to-digital converter, and a hybrid loop filter that contains an analog feedforward path and digital integrating path. In addition, an all-digital frequency acquisition method that does not require a reference frequency, quadrature phases from the VCO, or a significant amount of high-speed logic is presented. A nice byproduct of the frequency acquisition circuitry is that it also provides an estimate of the bit error rate (BER) experienced by the CDR. The CDR exceeds all SONET performance requirements at 155-, 622-, and 2500-Mb/s as well as Gigabit Ethernet specifications at 1.25 Gb/s. The chip operates with either a 2.5-or 3.3-V supply, consumes a maximum of 197 mA across all data rates, and fits in a 5 5 mm package.

A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit

Analog Integrated Circuits and Signal Processing, 2007

A fully-integrated 5 Gb/s PLL-based clock and data recovery circuit based on a linear half-rate phase detector (PD) architecture is presented. Data retiming performed by the linear PD provides practically no systematic offset for the operating frequency of interest. The circuit was designed in a 0.18 lm CMOS process and occupies an active area of 0.2 • 0.32 mm 2. The CDR exhibits an RMS jitter of ± 1.2 ps and a peak-to-peak jitter of 5 ps. The power dissipation is 97 mW from a 1.8 V supply.

A 200-Mbps∼2-Gbps continuous-rate clock-and-data-recovery circuit

IEEE Transactions on Circuits and Systems I-regular Papers, 2006

A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems

IEEE Journal of Solid-State Circuits, 2003

A 43-Gb/s receiver (Rx) and transmitter (Tx) chip set for SONET OC-768 transmission systems is reported. Both ICs are implemented in a 0.18-m SiGe BiCMOS technology featuring 120-GHz and 100 GHz max . The Rx includes a limiting amplifier, a half-rate clock and data recovery unit, a 1:4 demultiplexer, a frequency acquisition aid, and a frequency lock detector. Input sensitivity for a bit-error rate less than 10 9 is 40 mV and jitter generation better than 230 fs rms. The IC dissipates 2.4 W from a 3.6-V supply voltage. The Tx integrates a half-rate clock multiplier unit with a 4:1 multiplexer. Measured clock jitter generation is better than 170 fs rms. The IC consumes 2.3 W from a 3.6-V supply voltage. Index Terms-Clock and data recovery (CDR), clock multiplier, phase detector, SiGe BiCMOS. I. INTRODUCTION K EY BUILDING block ICs operating beyond 40-Gb/s data rate, such as multiplexers, demultiplexers, or retiming flip-flops, have already been reported in the literature [1], [2]. Highly integrated ICs such as receivers and transmitters showing adequate system-level performance in terms of jitter, bit-error rate (BER), and signal integrity have been reported only recently [3]-[6] . However, the required performance is achieved at the expense of high power consumption, particularly when sufficient design margins are sought. This is mainly due to the frequency capabilities of today's production-level technologies, which seem to be marginal for such high operating speeds. As a consequence, half-rate clocking schemes are in general chosen over full-rate clocking schemes; full-rate schemes stress technology limits and are more power hungry than half-rate schemes. However, compared with full-rate architectures, half-rate architectures present several new challenges. Clock and data recovery (CDR) circuits require quadrature clocks and present difficult clock distribution because of higher fan-out. Half-rate architectures are also more sensitive to jitter generation and jitter tolerance requirements because the phase detector (PD) has higher latency and is very sensitive to clock duty cycle distortion and quadrature clock phase matching. Finally, time-division multiplexers do not include a final retiming stage operating on a single edge of the clock, and thus the half-rate clock duty cycle distortion directly impacts the serial data output duty cycle.