Mixed abstraction level hardware synthesis from SDL for rapid prototyping (original) (raw)

VHDL generation from SDL specifications

1996

The aim of this paper is to present an approach that allows the generation of VHDL from system level speci cations in SDL. Our approach o vercome the main known problem encountered by previous work which is the communication between di erent processes. We allow SDL communication to be translated into VHDL for synthesis. This is made possible by t h e u s e o f a n intermediate form that support a powerful communication model which e nable the representation in a synthesis oriented manner of most communication schemes. This intermediate form allows the re nement of the system in order to obtain the desired solution. The main re nement step, called communication synthesis, is aimed at xing the protocol and the interface used by t h e di erent processes to communicate. The re ned speci cation is translated into VHDL for synthesis using existing CAD tools. We illustrate the feasibility o f our approach through two SDL to VHDL translation examples.

Modeling of Embedded Digital Systems from SDL Language: a Case Study

2002

Abstract The goal of this paper is to evaluate the performance of digital systems generated from a high-level description language. The target language in this work is SDL. The SDL description is automatically synthesized with a codesign tool, resulting in a VHDL description. The codesign tool is responsible for software, hardware and communication synthesis.

VHDL-based rapid system prototyping

Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 1996

The Rapid Prototyping of Application-Specific Signal Processors (RASSP) [1–3] program of the US Department of Defense (ARPA and Tri-Services) targets a 4X improvement in the design, prototyping, manufacturing, and support processes (relative to current practice). Based on a current practice study (1993) [4], the prototyping time from system requirements definition to production and deployment, of multiboard signal processors, is between 37 and 73 months. Out of this time, 25–49 months is devoted to detailed hardware/software (HW/SW) design and integration (with 10–24 months devoted to the latter task of integration). With the utilization of a promising top-down hardware-less codesign methodology based on VHDL models of HW/SW components at multiple abstractions, reduction in design time has been shown especially in the area of hardware/software integration [5]. The authors describe a top-down design approach in VHDL starting with the capture of system requirements in an executable form and through successive stages of design refinement, ending with a detailed hardware design. This hardware/software codesign process is based on the RASSP program design methodology called virtual prototyping, wherein VHDL models are used throughout the design process to capture the necessary information to describe the design as it develops through successive refinement and review. Examples are presented to illustrate the information captured at each stage in the process. Links between stages are described to clarify the flow of information from requirements to hardware.

Compiling VHDL into a high-level synthesis design representation

European Design and Test Conference, 1992

The paper discusses the problem of extending the use of VHDL to the field of hardware synthesis.The main difficulty lies in the fact that the semantics of standard VHDL is defined strictly in terms of simulation. We present a synthesis-oriented compiler based on a broad subset of VHDL. We describe the language subset, the internal design representation (based on an

Automated digital hardware synthesis using VHDL

1991

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Sast: An interconnection aware high-level synthesis tool

Proc. 9th VLSI Design …, 2005

Today's VLSI technology allows us to construct large, complex systems with million transistors on a single chip. Most of the existing high level synthesis systems give more priority to optimization of area, power, resource and time steps compared to interconnection cost, whereas the later becomes predominant with the technology scaling and increase in complexity. Further, field programmable gate arrays (FPGA) are now becoming attractive platform for prototyping. Programmable devices tend to have limited wiring resources between the data path elements. This work is concerned with the development of a CAD tool for HLS named, "Structured Architecture Synthesis Tool (SAST)", which incorporates structured architecture generation with special emphasis on optimization of interconnect area. The too takes a behavioral description written in 3-address form and generates synthesizable RTL codes with scripts for compliance with standard design tools like Synopsys, Magma etc.

Design Progression With VHDL Helps Accelerate The Digital System Designs

2006

Integrated Circuit technology (IC) is the enabling technology for a whole host of innovative devices a nd systems that have changed the way we live. Integrat d Circuits are much smaller and consume less power than the discrete components used to build electron i systems before the 1960s. Integrated circuits ar e also easier to design and manufacture and are more reliable than discrete systems. The growing sophistication of applications continually pushes t he design and manufacturing of integrated circuits and electronic systems to new levels of complexity. Due to major advances in the development of electronic s and miniaturization, vendors are capable of buildin g and designing products with increasingly greater functionality, higher performance, lower cost, lowe r power consumption, and smaller dimensions [1]. However, the bottleneck for some vendors appears to be the ability of designers to target the necessar y increase in the complexity of electronic devices. F urthermore, the...

Design procedure based on VHDL language transformations

1999

Abstract Automated hardware synthesis starting from the register transfer level (RT-level) VHDL description is well established. However, starting the design on a higher abstraction level than the RT-level is one of the major problems within the VHDL based system synthesis. We present a novel design procedure called SYLANT (Synthesis based on Language Transformations), which uses the methodology of high-level synthesis.

High-level synthesis: productivity, performance, and software constraints

2012

Abstract FPGAs are an attractive platform for applications with high computation demand and low energy consumption requirements. However, design effort for FPGA implementations remains high--often an order of magnitude larger than design effort using high-level languages. Instead of this time-consuming process, high-level synthesis (HLS) tools generate hardware implementations from algorithm descriptions in languages such as C/C++ and SystemC.

High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain

2014 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

High-Level Synthesis (HLS) is an automated design process that deals with the generation of behavioral hardware descriptions from high-level algorithmic specifications. The main benefit of this approach is that ever-increasing system-on-chip (SoC) design complexity and ever-shorter time-to-market can still be both manageable and achievable. This advantage, coupled with the increasing number of available heterogeneous platforms that loosely couple general-purpose processors with Field-Programmable Gate Array (FPGA)-based co-processors, led to an increasing attention for HLS tool development and optimization from both the academia as well as the industry. However, in order for HLS to fully reach its potential, it is imperative to look simultaneously at local HLS optimizations as well as to HLS system-level integration and design space exploration issues. In this paper, we present the Delft Workbench tool-chain that takes C-code as input and generates, in a semiautomatic way, a complete system. Subsequently, we describe the design and output code optimization of the DWARV 3.0 HLS compiler using the CoSy compiler framework. Based on this experience, we provide an overview of similarities and differences in leveraging this commercial compiler framework to build a hardware compiler as opposed to building a software compiler. Finally, we report speedups up to 3.72x at application level and development times measurable in hours rather than weeks.