Automated substrate resistance extraction in nanoscale VLSI by exploiting a geometry-based analytical model (original) (raw)

Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems Mixdes 2011, 2011

Abstract

In this work, a new automated method for determining the substrate resistance is presented. It exploits a geometric formulation of the current streamlines between coupled structures and builds an analytical model for the substrate resistance. Both simulation and measurement data are utilized in order to show the validity of the proposed scheme. The measurement data are obtained from a fabricated test chip. The results show that the proposed method succeeds in computing the substrate resistance while the average error falls within 5%. Index Terms—Substrate noise; Integrated circuits; geometric modeling; Resistance extraction; Resistance Modeling; Parasitics.

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