Performance analysis of variable packet size crosspoint-queued switch (original) (raw)
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The performance analysis of the 32x32 crosspoint queued switch is presented in this paper. Switches with small buffers in crosspoints have been evaluated in the late Eighties, but mostly for uniform traffic. However, due to technological limitations of that time, it was impractical to implement large buffers together with switching fabric. The crosspoint queued switch architecture has been recently brought back into focus since modern technology enables an easy implementation of large buffers in crosspoints. An advantage of this solution is the absence of control communication between linecards and schedulers. In this paper, the performances of four algorithms (longest queue first, round robin, exhaustive round robin and frame based round robin matching), are analyzed and compared. The results obtained for the crosspoint queued switch are compared with the output queued switch. Throughput, average cell latency and instantaneous packet delay variance are evaluated under uniform and nonuniform traffic patterns.
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ARCHITECTURE DESIGN AND PERFORMANCE ANALYSIS OF PRACTICAL BUFFERED-CROSSBAR PACKET SWITCHES by Ziqian Dong Combined input crosspoint buffered (CICB) packet switches were introduced to relax inputoutput arbitration timing and provide high throughput under admissible traffic. However, the amount of memory required in the crossbar of an N x N switch is N2 x k x L, where k is the crosspoint buffer size and needs to be of size RTT in cells, L is the packet size. RTT is the round-trip time which is defined by the distance between line cards and switch fabric. When the switch size is large or RTT is not negligible, the memory amount required makes the implementation costly or infeasible for buffered crossbar switches. To reduce the required memory amount, a family of shared memory combined-input crosspoint-buffered (SMCB) packet switches, where the crosspoint buffers are shared among inputs, are introduced in this thesis. One of the proposed switches uses a memory speedup of 711 and dynami...
Long Round-Trip Time Support with Shared-Memory Crosspoint Buffered Packet Switch
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The amount of memory in buffered crossbars in combined input-crosspoint buffered switches is proportional to the number of crosspoints, or O(N 2 ), where N is the number of ports, and to the crosspoint buffer size, which is defined by the distance between the line cards and the buffered crossbar, to achieve 100% throughput under port-rate data flows. A long distance between these two components can make a buffered crossbar costly to implement. In this paper, we propose and examine two shared-memory crosspoint buffered packet switches that use small crosspoint buffers to support a long round-trip time, which is mainly affected by the transmission delay caused by the distance between line cards and the buffered crossbar. The proposed switch reduces the required buffer memory of the buffered crossbar by 50% or more. We show that a sharedmemory crosspoint buffer switch can provide high this improvement without speedup.
Shared-Memory Combined Input-Crosspoint Buffered Packet Switch for Differentiated Services
… Conference, 2006. GLOBECOM'06. …, 2006
Combined input-crosspoint buffered (CICB) packet switches with dedicated crosspoint buffers require a minimum amount of memory in the buffered crossbar of N 2 × k × L, where N is the number of ports and k is the crosspoint buffer size, which is defined by the distance between the line cards and the buffered crossbar, to achieve 100% throughput under highspeed data flows. A long distance between these two components can make a buffered crossbar costly to implement. In this paper, we study a shared-memory crosspoint buffered packet switch that uses small crosspoint buffers and no speedup to support differentiated services and long distances between the line cards and the buffered crossbar in practical implementations. The proposed switch requires a buffer memory of 1 m of that in a CICB switch with dedicated crosspoint buffers to achieve similar throughput performance to that of a CICB switch.