Building timing predictable embedded systems (original) (raw)

2014, ACM Transactions on Embedded Computing Systems

Saarland Univ., 5: Uppsala Univ., 6: TU Dortmund, 7: Univ. of Toulouse, 8: CAU Kiel A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori. Perhaps paradoxically, this problem has become more difficult by the introduction of performanceenhancing architectural elements, such as caches, pipelines, and multithreading, which introduce a large degree of uncertainty and make guarantees harder to provide. The intention of this paper is to summarize the current state of the art in research concerning how to build predictable yet performant systems. We suggest precise definitions for the concept of "predictability", and present predictability concerns at different abstraction levels in embedded system design. First, we consider timing predictability of processor instruction sets. Thereafter, we consider how programming languages can be equipped with predictable timing semantics, covering both a language-based approach using the synchronous programming paradigm, as well as an environment that provides timing semantics for a mainstream programming language (in this case C). We present techniques for achieving timing predictability on multicores. Finally, we discuss how to handle predictability at the level of networked embedded systems where randomly occurring errors must be considered.

Predictable Programming on a precision timed architecture

Embedded Systems Week 2008 - Proceedings of the 2008 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES'08, 2008

In a hard real-time embedded system, the time at which a result is computed is as important as the result itself. Modern processors go to extreme lengths to ensure their function is predictable, but have abandoned predictable timing in favor of average-case performance. Real-time operating systems provide timing-aware scheduling policies, but without precise worst-case execution time bounds they cannot provide guarantees.

Towards Timing Predictability and Composability

2009

As real-time software is increasing in size and complexity, the need for advanced modeling and analysis capabilities early in the software development process is getting more and more urgent. One particular concern is the lack of sufficient methods and tools to effectively reason about the timing of software in such a way that software systems can be constructed hierarchically from components while still guaranteeing the timing properties [1].

Architecture for Predictable Systems

Predictable systems are systems in which correctness arguments consider both the appropriateness and the timeliness of delivered results. Such systems exhibit both statistical timing as well as bounded duration timing ex- pectations. Such systems require suitable architectural techniques that do not preclude meeting the timing ex- pectations. This paper provides a summary of some of these issues and the architectural concerns that surface when addressing timing constraints in performance critical systems. The currently well-known design meth- ods are examined for their suitability to describe and re- cord architectures with predictable performance. Rele- vant changes resulting in a suitable method for real-time object-oriented analysis to are suggested.

Processor Support for Temporal Predictability - The SPEAR Design Example

The demand for predictable timing behavior is characteristic for real-time applications. Experience has shown that this property cannot be achieved by software alone but rather requires support from the processor. This situation is analyzed and mapped to a design rationale for SPEAR (Scalable Processor for Embedded Applications in Real-time Environments), a processor that has been designed to meet the specific temporal demands of real-time systems. At the hardware level, SPEAR guarantees interrupt response with minimum temporal jitter and minimum delay. Furthermore, the processor provides an instruction set that only has constant-time instructions. At the software level, SPEAR supports the implementation of temporally predictable code according to the single-path programming paradigm. Altogether, these features support writing of code with minimal jitter and provide the basis for exact temporal predictability. Experimental results show that SPEAR indeed exhibits the anticipated high...

Programs with ironclad timing guarantees

Proceedings of the International Conference on Embedded Software Companion - EMSOFT '19, 2019

We discuss ongoing work towards a metalanguage , execution model, and compiler tool chain that promotes determinism and grants first-class citizenship to the timing aspects of computation. CCS CONCEPTS • Computer systems organization → Real-time languages; Real-time system specification; Embedded systems;

Loading...

Loading Preview

Sorry, preview is currently unavailable. You can download the paper by clicking the button above.