Correlation between Gate Length, Geometry and Electrostatic Driven Performance in Ultra-Scaled Silicon Nanowire Transistors (original) (raw)

Influence of quantum confinement effects over device performance in circular and elliptical silicon nanowire transistors

This work reveals the impact of quantum mechanical effects on the device performancce of n-type silicon nanowire transistors (NWT). Here we present results for two Si NWTs with circular and elliptical cross-section. Additionally we designed both devices to have identical cross-section in order to provide fair comparison. Also we extended our discussions by reporting devices with five different gate lengths for both circular and elliptical nanowires. Our calculations gave us the opportunity to establish a link between the charge distribution in the channel, gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). We also performed two types of calculations considering two different theoretical approaches. First one is based on drift-diffusion (DD) without quantum correction. The second one is constructed on quantum mechanical (QM) description of the mobile charge distribution in the channel. The QM methodology is based on Schr??dinger equation. More importantly, in this work showw that capturing the QM effects is mandatory for nanowires with such ultra-scale dimensions.

Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of N-type Nanowire Transistors

In this paper we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWT) for application in advanced CMOS technologies. The 3D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2D cross-sections along the direction of the transport are presented. The simulated NWTs have cross-sections and dimensional characteristics representative of the transistors expected at 7nm CMOS technology. Different gate lengths, cross-section shapes, spacer thicknesses and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, the mobile charge in the channel, the drain-induced barrier lowering and the sub-threshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs is also investigated. We have also estimated the optimal gate length for different NWT design conditions.

Orientation dependence of the charge distribution and quantum capacitance in silicon nanowire transistors

2008

Abstract CMOS devices are evolving from planar to 3D non-planar devices at nanometer scale to meet the ITRS [1] scaling requirements. These devices will operate under strong confinement and strain, regimes where atomistic effects are important. This work focuses on the quantum effects on the electrostatics of ultra-scaled silicon nanowire transistors. The method is based on the calculation of nanowire dispersion using an atomistic tight-binding (TB) model (sp3d5s*-SO) coupled self-consistently to a 2D Poisson equation solver.

A Technological Review on Quantum Ballistic Transport Model Based Silicon Nanowire Field Effect Transistors for Circuit Simulation and Design

Journal of NanoScience, NanoEngineering & Applications, ISSN: 2231-1777(online), ISSN: 2321-5194(print) Volume 5, Issue 2, 2015

Nanowire MOSFETs are recognized as one of the most promising candidates to extend Moore’s law into nanoelectronics era. This paper reviews the process, application, device physics and compact modeling of Gate All around (GAA) nanowire MOSFETs. The most widely used methods of nanowire synthesis have been discussed. The paper presents the various device optimization techniques and scaling potential of nanowire transistors. A process sensitivity study of silicon nanowire transistors at the end of the paper justifies the theory of nanowire FETs to carry forward the downscaling of MOSFETs in the sub-10 nm regime.

Influence of quantum confinement effects and device electrostatic driven performance in ultra-scaled Si x Ge 1-x nanowire transistors

In this work we have investigated the impact of quantum mechanical effects on the device performance of n-type in ultra-scaled SixGe1-x nanowire transistors (NWT) for possible future applications. For the purpose of this paper SixGe1-x NWTs with different SixGe1-x molar fraction has been simulated. However, in all devices the cross-sectional area, dimensions and doping profiles are kept constant in order to provide fair comparison. The design of computational experiment in this work includes nanowire transistors with different gate length of 6nm, 8nm, 10nm, 12nm and 14nm. All wires are simulated with various SixGe1-x ratio. As a result we have established a correlation between the mobile charge distribution in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also have been investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrödinger equation, which is indeed preferred approach for nanowires with such ultra-scale dimensions.

Impact of strain on the performance of Si nanowires transistors at the scaling limit: A 3D Monte Carlo / 2D Poisson Schrodinger simulation study

In this work we investigate the correlation between channel strain and device performance in various n-type Si-NWTs. We establish a correlation between strain, gate length and cross-section dimension of the transistors. For the purpose of this paper we simulate Si NWTs with a <110> channel orientation, four different ellipsoidal channel cross-sections and five gate lengths: 4nm, 6nm, 8nm, 10nm and 12nm. We have also analyzed the impact of strain on drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All simulations are based on a quantum mechanical description of the mobile charge distribution in the channel obtained from a 2D solution of the Schrödinger equation in multiple cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions. The current transport along the channel is simulated using 3D Monte Carlo (MC) and drift-diffusion (DD) approaches.

Quantum simulation study of gate-all-around (GAA) silicon nanowire transistor and double gate metal oxide semiconductor field effect transistor (DG MOSFET)

International Journal of the Physical Sciences, 2012

In this paper, electrical characteristics of the double gate metal oxide semiconductor field effect transistor (DG MOSFET) and that of gate all around silicon nanowire transistor (GAA SNWT) have been investigated. We have evaluated the variations of the threshold voltage, the subthreshold slope, draininduced barrier lowering, ON and OFF state currents when channel length decreases. Quantum mechanical transport approach based on non-equilibrium Green's function method (NEGF) has been performed in the frame work of effective mass theory with taking into account exchange-correlation effects. Its simulation consists of solutions of the three dimensional Poisson's equation, two dimensional Schrodinger equation on the cross section plane, and also transport equation. We have shown that for lengths smaller than 15 nm, short channel effects dominate. When the dimensions become smaller, interelectronic distance decreases and the interaction between electrons and also exchange correlation effects increase. We have also demonstrated that short channel effects are decreased using the device which has a good control of gate.