Design of a Reversible Floating-Point Adder Architecture (original) (raw)

A Low Quantum Cost Implementation of Reversible Binary-Coded-Decimal Adder

Periodica Polytechnica Electrical Engineering and Computer Science

The prediction and forthcoming of a quantum computer into the real-world is the much gained research area over the last decades, which initiated the usefulness and profit of reversible computation because of its potentiality to reduce power consumption in designing arithmetic circuits. In this paper, two design approaches are proposed for the design of a reversible Binary-Coded-Decimal adder. The first approach is implemented and realized from reversible gates proposed by researchers in the technical literature capable of breaking down into primitive quantum gates, whereas the second approach is realized from the existing synthesizable reversible gates only. Parallel implementations of such circuits have been carried out through the proper selection and arrangements of the gates to improve the reversible performance parameters. The proposed design approaches offer a low quantum cost along-with lower delay and hardware complexity for any n-digit addition. Analysis results of proposed...

Full Adder/ Subtractor Using Reversible Logic

2019

Reversible logic is now-a-days emerging as an im-portantresearch area over conventional logic. It is having varietyof applications in fields of Digital Signal Processing, QuantumComputing and Low Power CMOS Design. Irreversiblelogic circuits dissipate heat for every bit of information thatis lost. It is not possible to think of quantum computingwithout implementation of reversible logic. The main purposesof designing reversible logic are to decrease quantumcost, depth of the circuits and the number of garbage outputs.This paper provides the Full adder/subtractor thatuses Half adder/ subtractor with minimum constant inputsand minimum garbage outputs. Thus the proposed architectureFull Adder/ Subtractor is having minimum numberof Constant Inputs and Garbage Outputs than the Existingarchitecture.

Efficient approaches for designing reversible Binary Coded Decimal adders

Microelectronics Journal, 2008

Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low-power CMOS, nanocomputing and optical computing. This paper presents improved and efficient reversible logic implementations for Binary Coded Decimal (BCD) adder as well as Carry Skip BCD adder. It has been shown that the modified designs outperform the existing ones in terms of number of gates, number of garbage outputs, delay, and quantum cost. In order to show the efficiency of the proposed designs, lower bounds of the reversible BCD adders in terms of gates and garbage outputs are proposed as well.

Design of Efficient Reversible Parallel Binary Adder/Subtractor

In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing etc. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible 8-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number gates, Garbage inputs / outputs and Quantum Cost. It is observed that Reversible 8-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I and II.

Low Power Reversible Parallel Binary Adder/Subtractor

In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.

Design of a compact reversible binary coded decimal adder circuit

Journal of Systems Architecture, 2006

Reversible logic is an emerging research area and getting remarkable interests over the past few years. Interest is sparked in reversible logic by its applications in several technologies, such as quantum, optical, thermodynamics and adiabatic CMOS. This paper represents a synthesis method to realize reversible binary coded decimal adder circuit. Firstly, a reversible full-adder circuit has been proposed that shows the improvement over the two existing circuits. A lower bound is also proposed for the reversible full-adder circuit on the number of garbage outputs (bits needed for reversibility, but not required for the output of the circuit). After that, a final improvement is presented for the reversible full-adder circuit. Finally, a new reversible circuit has been proposed, namely reversible binary coded decimal (BCD) adder, which is the first ever proposed in reversible logic synthesis. In the way to propose reversible BCD adder, a reversible n-bits parallel adder circuit is also shown. Lower bounds for the reversible BCD adder in terms of number of garbage outputs and number of reversible gates are also shown. Delay has also been calculated for each circuit.

Towards Efficient Modular Adders based on Reversible Circuits

Reversible logic is a reckoning standard that has attracted momentous attention in recent years due to its properties that lead to ultra-low-power reliable circuits. Reversible circuits are fundamental in executing quantum computing. Since addition is an essential operation in designing efficient adders it is a key element in the research of reversible circuits. RNS has been an influential tool to come up with parallel and fault-tolerant implementations of computations in which additions and multiplications are assertive. In our project, we have implemented a combination of RNS and reversible logic. The parallelism of RNS is highly influential to increase the accomplishment of reversible computational circuits. Since modulo adders play a pivotal role in any RNS, we here proposed modular adders using reversible logic. The proposed adders have been synthesized using Xilinx tool and from the experimental results it is identified that modulo adders could be designed by means of reversible gates with minimum expenditure in assessment to regular reversible adders.

A LOW POWER ADDER USING REVERSIBLE LOGIC GATES

IJRET, 2012

Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In contrast to conventional gates, reversible logic gates have the same number of inputs and outputs, each of their output function is equal to 1 for exactly half its input assignments and their fan-out is always equal to 1. It is interesting to compare both reversible and conventional gates. In this paper addition, subtraction, operations are realized using reversible logic gates like DKG and TSG gate and compared with conventional gates

Efficient Design Of 4-Bit Binary Adder Using Reversible Logic Gates

This paper proposes the design of 4-bit adder and implementation of adder Reversible logic gate to improve the design in terms of garbage outputs and delay. In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology and optical computing because of it’s zero power dissipation under ideal conditions. Thus, the project will provide the reversible logic implementation of the conventional 4-bit adder using Toffoli gate, Peres gate and using both Peres gate and Fredkin gate. The proposed reversible logic implementation of the 4- bit adder is optimized to obtain minimum number of logic gates and garbage outputs. This project work on the reversible 4-bit adder circuits designed and proposed here form the basis of the decimal ALU of a primitive quantum CPU. The designed and optimized 4-bit reversible adder is implemented in VHDL Using Xilinx ISE 12.1 tool.