Thermal effects of die-attach voids location and style on performance of chip level package (original) (raw)

2011

Abstract

... KC Otiaba*, RS Bhatti, NN Ekere, S. Mallik, EH Amalu & M. Ekpu Electronics Manufacturing Engineering Research Group, University of ... [14]. Laxmidhar Biswal, Arvind Krishna, Doug Sprunger, Effect of Solder Voids on Thermal Performance of a High Power Electronic Module. ...

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