Efficient and Accurate Analysis of Single Event Transients Propagation Using SMT-Based Techniques (original) (raw)
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The effect of Single-Event Transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of a combinational part of a circuit may propagate as a transient pulse at the input of a flip-flop and consequently latches in the flip-flop; thus generating a soft-error. When an SET is combined with a transition at a node (i.e., dynamic behavior of that node) along a critical path of the combinational part of a design, a transient delay fault may occur at the input of a circuit flip-flop. Using the Probability Density Function (PDF) of an SET, this paper proposes a statistical method to compute the probability of soft-errors caused by SETs considering dynamic behavior of a circuit.
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Integrated circuit susceptibility to radiation-induced faults remains a major reliability concern. The continuous downscaling of device feature size and the reduction in supply voltage in CMOS technology tend to worsen the problem. Thus, the evaluation of Soft Error Rate (SER) in the presence of multiple transient faults is necessary, since it remains an open research field. In this work, a Monte-Carlo simulation-based methodology is presented taking into consideration the masking mechanisms and placement information. The proposed SER estimation tool exploits the results of a Single Event Transient (SET) pulse characterization process with HSPICE to obtain an accurate assessment of circuit vulnerability to radiation. A new metric, called Glitch Latching Probability, which represents the impact of the masking effects on a SET, is introduced to identify gate sensitivity and, finally, experimental results on a set of ISCAS’ 89 benchmarks are presented.
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