A GALS Router for Asynchronous Network-on-Chip (original) (raw)

Power comparison of an asynchronous and synchronous network on chip router

International Journal of Radiation Oncology Biology Physics, 2004

This paper presents an asynchronous and a synchronous NoC router architecture. The asynchronous scheme is implemented by the help of CSP-Verilog language and the synchronous one is designed employing VHDL language. Their designs are similar except the extra links which are in charge of handshaking processes in asynchronous architecture. According to the experimental results the transition counts of buffer, and switch components in synchronous router are almost 82% and 60% of asynchronous one, respectively. On the other hand, the transition counting of routing unit in asynchronous NoC router is nearly 73% of synchronous one. Power consumption of them are evaluated according to the obtained transition counting. Based on the comparison the power consumption of buffer and switch components are almost same due to their similar structure. However, the power consumption of routing unit component in asynchronous design is lower than synchronous one.

Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping

IFIP International Federation for Information Proc, 2007

This paper presents an innovating methodology for fast and easy design of Asynchronous Network-on-Chips (ANoCs) dedicated to GALS systems. A topologyindependent building-block approach permits to design modular, scalable and reliable ANoCs with low-power and low-complexity requirements. A crossbar generator is added to the existing design flow for fast system architecture exploration. A multi-clock FPGA allows a fast prototyping of a complex ANoC-centric GALS system. It includes synchronous standard IP cores and asynchronous modules connected through an asynchronous 5x5 crossbar. First results about communication costs/performances across the Asynchronous NoC are reported.

Hermes-glp: A gals network on chip router with power control techniques

Symposium on VLSI, …, 2008

The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-established design practices. Examples are the use of multi-point communication architectures (e. g. busses) and designing fully synchronous systems. In addition, power dissipation is becoming one of the main design concerns due e. g. to the increasing use of mobile products. An alternative to overcome such problems is adopting Networks on Chip (NoCs) communication architectures supporting globally asynchronous locally synchronous (GALS) system design. This work proposes a GALS router with associated power control techniques, which enables low power SoC design. This is in contrast with previous works which centered attention in power reduction of SoC processing elements instead. The paper describes the asynchronous communication interface and the employed power control mechanism. The results obtained from simulation at the RTL level with timing show that, even when submitted to large rates of traffic injection, the proposed NoC displays a significant reduction in switching activity and consequently in power dissipation.

Hermes-A–An Asynchronous NoC Router with Distributed Routing

Integrated Circuit and System …, 2011

This work presents the architecture and ASIC implementation of Hermes-A, an asynchronous network on chip router. Hermes-A is coupled to a network interface that enables communication between router and synchronous processing elements. The ASIC implementation of the router employed standard CAD tools and a specific library of components. Area and timing characteristics for 180nm technology attest the quality of the design, which displays a maximum throughput of 3.6 Gbits/s.

Reducing NoC Energy Consumption Exploring Asynchronous End-to-end GALS Communication

2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI), 2020

Systems-on-Chip (SoCs) with a large number of cores adopt Networks-on-chip (NoCs) as the communication infrastructure due to its scalability. The complexity to distribute a skew-free synchronous clock signal over the entire chip increases in current fabrication technologies due to the process variability. Thus, designers may choose among fully asynchronous and Globally Asynchronous, Locally Synchronous (GALS) NoCs. This work proposes an intermediate solution. Each Intellectual Property (IP) core may have its clock domain, and the NoC supports both synchronous and asynchronous communication. The NoC has its own clock domain, with the synchronous communication used to establish end-to-end paths. Once the end-to-end path is established, the NoC connects the IPs asynchronously, as wires with repeaters. The message is transmitted using handshake protocol at the source IP frequency. The benefit of the proposal is the reduction in the communication energy consumption (up to 52%). The cost is a latency increase (16% to 30%) and area overhead (4%). Index Terms-NoC, GALS, asynchronous communication, clock domain crossing.

A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000

A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global clock distribution, and can interface multiple synchronous timing domains operating at unrelated clock rates. In particular, two new highly-concurrent asynchronous components are introduced which provide simple routing and arbitration/merge functions. Post-layout simulations in identical commercial 90nm technology indicate that comparable recent synchronous router nodes have 5.6-10.7x more energy per packet and 2.8-6.4x greater area than the new asynchronous nodes. Under random traffic, the network provides significantly lower latency and competitive throughput over the entire operating range of the 800 MHz network and through mid-range traffic rates for the 1.36 GHz network, but with degradation at higher traffic rates. Preliminary evaluations are also presented for a mixedtiming (GALS) network in a shared-memory parallel architecture, running both random traffic and parallel benchmark kernels, as well as directions for further improvement. Sync Sync Sync Sync Sync Sync Sync Sync Mixed−Timing Network

An asynchronous router for multiple service levels networks on chip

11th IEEE International Symposium on Asynchronous Circuits and Systems, 2005

Networks on chip that can guarantee quality of service (QNoC) are based on special routers that can support multiple service levels. GALS SoCs call for asynchronous NoC implementations, to eliminate the need for synchronization when crossing clock domains. An asynchronous multi-service level QNoC router is investigated. It comprises multiple interconnected input and output ports, and arbitration mechanisms that resolve any output port and service level conflicts. Buffering and credit based transport are enabled, enhancing throughput. A synchronous and an asynchronous router have been designed, and their performance is compared. The asynchronous router requires less area and enables a higher data rate.

An asynchronous low-power innovative network-On-chip including design-for-test capabilities

2009 International Conference on Advanced Technologies for Communications, 2009

The demands of scalable, low latency and power efficient System-On-Chip interconnect cannot be satisfied only by point-to-point or shared-bus interconnects. By providing more bandwidth at reasonable power consumption, new communication infrastructures like NoCs seem promising, but are still limited by implementation issues. We present in this paper an Asynchronous Network-on-Chip architecture with two main innovations. Firstly, an automatic power regulation scheme is proposed to dynamically save leakage and dynamic power consumption. Secondly, due to the current lack of testing methodology for asynchronous logic, we propose a novel DfT solution to allow acceptance of the asynchronous NoC. The proposed architecture has been fully implemented in a STMicroelectronics CMOS 65nm technology, integrated in a complex test-chip and fabricated.