Phase Locked Loop Design for Fast Phase and Frequency Acquisition (original) (raw)

The specific property of fast locking of PLL is required in many clock and data recovery circuits. The most versatile application of the phase locked loops (PLL) is for clock generation and clock recovery in microprocessor, networking, communication systems, and frequency synthesizers. Phase locked-loops (PLLs) are commonly used to generate well-timed on-chip clocks in high performance digital systems. Modern wireless communication systems employ Phase Locked Loop (PLL) mainly for synchronization, clock synthesis, skew and jitter reduction. Because of the increase in the speed of the circuit operation, there is a need of a PLL circuit with faster locking ability. Hence there is a necessity of a PLL which must operate in the GHz range with less lock time. This paper presented a PLL with redesigning of individual blocks. The PLL is designed using 180 nm CMOS technology for high performance with 1.8 V power supply. Keywords-Phase Locked Loop (PLL), Phase Frequency Detector (PFD), Charge Pump (CP), Low Pass Filter (LPF), Voltage Controlled Oscillator (VCO)

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