Performance Analysis of Low Power MIMO Decoding Accelerator using Euclidean Orthogonal Architecture (original) (raw)

This paper proposes the MIMO Decoder Accelerator which targets multiple-input-multiple output (MIMO) decoding tasks of orthogonal frequency-division multiplexing (OFDM) systems. The MIMO Decoding Accelerator is designed using a Way Tag Detection Unit to reduce the power consumption. The MIMO accelerator is a software-programmable device that specializes in MIMO decoding and MIMO signal processing for OFDM systems. The main objective of the proposed design of MIMO decoder accelerator is to reduce the power consumption in multichannel environment. The Way Tag Detection unit is designed instead of FSM controller. It is used to enable the clock signal. The performance analysis is done between the conventional design, QR Decomposition method and proposed method. The Power Consumption of the proposed MIMO Decoding Accelerator was measured to be 267 mW at a clock frequency of 100-MHz clock frequency off of a 1-V supply. When compared to the conventional method the power consumption is reduced by 10% in the proposed MIMO Decoding Accelerator.