Performance Analysis of Low Power MIMO Decoding Accelerator using Euclidean Orthogonal Architecture (original) (raw)

A Low-power and Low-complexity Baseband Processor for MIMO-OFDM WLAN Systems

Journal of Signal Processing Systems, 2010

This paper presents an energy-efficient design and the implementation results of a high speed two transmitter-two receiver multi-input multi-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN baseband processor. The proposed processor includes a bit-parallel processing physical layer convergence procedure (PLCP) processor which lowers system clock frequency. A costefficient MIMO spatial multiplexing (SM) symbol detector is also proposed in a physical medium dependent (PMD) processor. The proposed symbol detection algorithm is based on a sorted QR decomposition (SQRD) scheme followed by a maximum-likelihood (ML) test. The proposed algorithm shows enhanced performance compared to the conventional algorithms such as SQRD and ordered successive interference cancellation (OSIC) algorithms. The proposed baseband processor supports a maximum data rate of 130 Mbps at a 40 MHz operation frequency. The power consumptions of the PLCP processor are 27 mW and 93 mW for TX and RX modes, respectively, which are reduced by 70% compared with that of a common bit-serial architecture. The complexity of the symbol detector in the PMD processor is reduced by 18% compared with that of the conventional hardware architecture.

Architectural Optimizations for Low-Power-Best MIMO Decoders

IEEE Transactions on Vehicular Technology, 2009

Maximum-likelihood (ML) detection for higher order multiple-input-multiple-output (MIMO) systems faces a major challenge in computational complexity. This limits the practicality of these systems from an implementation point of view, particularly for mobile battery-operated devices. In this paper, we propose a modified approach for MIMO detection, which takes advantage of the quadratic-amplitude modulation (QAM) constellation structure to accelerate the detection procedure. This approach achieves low-power operation by extending the minimum number of paths and reducing the number of required computations for each path extension, which results in an order-of-magnitude reduction in computations in comparison with existing algorithms. This paper also describes the very-large-scale integration (VLSI) design of the low-power path metric computation unit. The approach is applied to a 4 × 4, 64-QAM MIMO detector system. Results show negligible performance degradation compared with conventional algorithms while reducing the complexity by more than 50%.

Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOS

This paper presents an energy efficient programmable hardware accelerator that targets multiple-input-multipleoutput (MIMO) decoding tasks of orthogonal frequency-division multiplexing (OFDM) systems. The work is motivated by the adoption of MIMO and OFDM by almost all existing and emerging high-speed wireless data communication systems. The accelerator was fabricated in 65-nm CMOS technology and occupies a core area of 2.48 mm 2 . It delivers full programmability across different wireless standards (i.e., WiFi, 3G-long term evolution, and WiMax) as well as different MIMO decoding algorithms (i.e., minimum mean square error, singular value decomposition, and maximum likelihood) with extreme energy efficiency. The energy efficiency of our MIMO accelerator chip was compared against dedicated application specific integrated circuits for 4 × 4 QR decomposition, 4 × 4 singular value decomposition, and 2 × 2 minimum mean square error decoding. Despite the programmable nature of our design, it delivered energy efficiencies that were 18% to 28% better than the dedicated solutions reported in the literature. This paper presents the VLSI implementation of the architecture discussed in [14]- . It discusses the implementation decisions and tradeoffs used to ensure minimum overall energy consumption of the resulting accelerator chip without sacrificing programmability. Given its programmability and extreme energy efficiency, the accelerator is an ideal solution for today's smart phones that implement multiple MIMO-OFDM waveforms on the same platform.

Architectural Optimizations for Low-Power $K$ -Best MIMO Decoders

IEEE Transactions on Vehicular Technology, 2000

Reviews on Algorithms and Architectures for Efficient Design of MIMO Accelerator

We surveyed about the design techniques of Multiple Input Multiple Output (MIMO) accelerator.The MIMO accelerator is a software programmable device that specializes in MIMO decoding and MIMO signal processing for Orthogonal Frequency Division Multiplexing systems(OFDM).It allows various algorithms to be easily implemented with a single hardware design. The accelerator is fully programmable within the domain of algorithms and functions needed to implement MIMO decoding for any arbitrary system or standards (i.e.,WiFi, LTE, etc.).To improve the system performance and reduce the complexity of the accelerator design some algorithms and architectures has been discussed here. The implementation of Field Programmable Gate Array(FPGA) architectures has been reviewed to minimize the overall energy/area consumption for the efficient design of accelerator hardware.

Recursive QR Decomposition Architecture for Mimo-Ofdm Detection Systems

Journal of Circuits, Systems and Computers, 2013

This paper presents a modified implementation of QR decomposition for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) detection based on the Givens rotation method. The QR decomposition hardware is constructed using the coordinate rotation digital computer (CORDIC) algorithm operating with fewer gate counts and lower power consumption than do triangular systolic array (TSA) structures. Accurate signal transmission is essential to wireless communication systems. Thus, a more effective data detection algorithm and precise channel estimation method play vital roles in MIMO systems. Implementing data detection with QR decomposition helps reduce the complexity of MIMO-OFDM detection. Implementation results reveal that the proposed recursive QR decomposition (RQRD) architecture has lower clock latency than do TSA structures, and has a smaller hardware area than do Gram–Schmidt structures.

Hardware Implementation of OFDM Transceiver Using Simulink Blocks for MIMO Systems

River Publishers, 2023

In wireless communication applications, the MIMO-OFDM system plays a vital role. The multiple inputs and multiple outputs components of the MIMO process were the focal points. The communication process aims to reduce energy consumption at the original transmission input signal level while also improving the effectiveness of wireless communication applications. The hardware-based VLSI architecture will be used to modify this technology. This architecture is designed to improve the performance of the transceivers in 802.11 MIMO-OFDM systems. This system uses Matlab Simulink software and a hardware FPGA board to construct a 4x4 MIMO OFDM architecture. Matlab simulation is used to convert VHDL code and verify the output for the VLSI simulation graph. To optimize the transmission timing in the MIMO architecture process, design the blocks in the Simulink unit and alter the block layout in the overall OFDM-MIMO unit, as well as build the sub-system functions. The hardware architecture for the Simulink 802.11 MIMO-OFDM system design is implemented using the system generator and Xilinx software. The design technique for optimizing the hardware program design process for MIMO encode and decode processes, as well as transceiver operations, uses VHDL code. The goal of the simulation is to organize the MIMO-OFDM blocks and increase the energy efficiency of wireless communication systems.

Enabling VLSI Processing Blocks for MIMO-OFDM Communications

VLSI Design, 2008

Multi-input multi-output (MIMO) systems combined with orthogonal frequency-division multiplexing (OFDM) gained a wide popularity in wireless applications due to the potential of providing increased channel capacity and robustness against multipath fading channels. However these advantages come at the cost of a very high processing complexity and the efficient implementation of MIMO-OFDM receivers is today a major research topic. In this paper, efficient architectures are proposed for the hardware implementation of the main building blocks of a MIMO-OFDM receiver. A sphere decoder architecture flexible to different modulation without any loss in BER performance is presented while the proposed matrix factorization implementation allows to achieve the highest throughput specified in the IEEE 802.11n standard. Finally a novel E 8 sphere decoder approach is presented, which allows for the realization of new golden space time trellis coded modulation (GST-TCM) scheme. Implementation cost and offered throughput are provided for the proposed architectures synthesized on a 0.13 μm CMOS standard cell technology or on advanced FPGA devices.

Design Of High Throughput MIMO Detectors with Hardware Efficient Architecture

MIMO-OFDM is the foundation for most advanced wireless local area network (Wireless LAN) and mobile broadband network standards. The efficient architecture of 4*4 64-QAM MIMO detectors are mainly used for the wireless communication. The existing architecture embedded large number of buffer memories, increases the chip area and power consumption. In order to reduce the area and power consumption novel error-resilient k-best MIMO detector architecture is used. This paper concentrates to modify the IPM processor and the PCM blocks in MIMO detector architecture. This optimization technique to reduce the power consumption and increase the speed also. The two-way sorting approach mainly used to reduce the power consumption level and also reduce the circuit complexity. This methodology to reduce the internal component level and to design the internal component in tree formation process and modified the child process. And find the minimum distance in the gate component architecture. MIMO detector architecture Synthesis and implementation is done by using Xilinx 14.2i Spartan 3E kit.

Design of Low Power Mixed Radix FFT Processor for MIMO OFDM Systems

A fast Fourier transform (FFT) is an efficient algorithm to compute the discrete Fourier transform (DFT) and its inverse. Computing a DFT of N points in the naive way, using the definition, takes O(N2) arithmetical operations, while an FFT can compute the same result in only O(N log N) operations. FFTs are of great importance to a wide variety of applications, from Digital Signal Processing to solving Partial Differential Equations. A pipelined Fast Fourier Transform and its inverse (FFT/IFFT) processor, which utilizes hardware resources efficiently, is proposed for MIMO-OFDM WLAN 802.11n. Compared with a conventional MIMO-OFDM implementation, in which as many FFT/IFFT processors as the number of transmit/receive antennas is used, the proposed architecture uses a single FFT processor with mixed radix and hence reduces hardware complexity without sacrificing system throughput. Further, the proposed architecture can support 1–4 simultaneous input data sequences with sequence lengths of 64 or 128, as needed. A theoretical study and computer simulation (MODELSIM) works of the 128/64 point FFT/IFFT processor is presented.

Performance Analysis of Low Power MIMO Decoding Accelerator using Euclidean Orthogonal Architecture (original) (raw)

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