A Large-Signal Graphene FET Model (original) (raw)
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A Comprehensive Graphene FET Model for Circuit Design
IEEE Transactions on Electron Devices, 2000
During the last years, Graphene based Field Effect Transistors (GFET) have shown outstanding RF performance; therefore, they have attracted considerable attention from the electronic devices and circuits communities. At the same time, analytical models that predict the electrical characteristics of GFETs have evolved rapidly. These models, however, have a complexity level that can only be handled with the help of a circuit simulator. On the other hand, analog circuit designers require simple models that enable them to carry out fast handcalculations, i.e., to create circuits using small-signal hybrid-π models, calculate figures of merit, estimate gains, pole-zero positions, etc. This paper presents a comprehensive GFET model that is simple enough for being used in hand-calculations during circuit design and at the same time it is accurate enough to capture the electrical characteristics of the devices in the operating regions of interest. Closed analytical expressions are provided for the drain current ID, small-signal transconductance gain gm, output resistance ro, and parasitic capacitances Cgs and C gd. In addition, figures of merit such as intrinsic voltage gain AV , transconductance efficiency gm/ID, and transit frequency fT are presented. The proposed model has been compared to a complete analytical model and also to measured data available in current literature. The results show that the proposed model follows closely to both the complete analytical model and the measured data; therefore, it can be successfully applied in the design of GFET analog circuits.
IEEE Transactions on Electron Devices, 2000
The analytical model of the small-signal current and capacitance characteristics of RF graphene FET is presented. The model is based on explicit distributions of chemical potential in graphene channels (including ambipolar conductivity at high source-drain bias) obtained in the framework of drift-diffusion current continuity equation solution. Small-signal transconductance and output conductance characteristics are modeled taking into account the two modes of drain current saturation including drift velocity saturation or electrostatic pinch-off. Analytical closed expression for the complex current gain and the cutoff frequency of high-frequency GFETs are obtained. The model allows describe an impact of parasitic resistances, capacitances, interface traps on extrinsic current gain and cut-off frequency.
2016
Transistors (GFET) have shown outstanding RF performance; therefore, they have attracted considerable attention from the electronic devices and circuits communities. At the same time, analytical models that predict the electrical characteristics of GFETs have evolved rapidly. These models, however, have a complexity level that can only be handled with the help of a circuit simulator. On the other hand, analog circuit designers require simple models that enable them to carry out fast hand-calculations, i.e., to create circuits using small-signal hybrid-pi models, calculate figures of merit, estimate gains, pole-zero positions, etc. This paper presents a comprehensive GFET model that is simple enough for being used in hand-calculations during circuit design and at the same time it is accurate enough to capture the electrical characteristics of the devices in the operating regions of interest. Closed analytical expressions are provided for the drain current ID, small-signal transconduc...
Source-Pull and Load-Pull Characterization of Graphene FET
IEEE Journal of the Electron Devices Society , 2015
This paper presents the characterization of a GFET transistor using a source-pull/load-pull test set. The characterization shows that despite the good f T and f MAX , it is hard to achieve power gain using the GFET device within a circuit configuration. This is due to the very high impedance at the gate making impedance matching at the input extremely difficult. S-parameter characterization is performed and the associated small signal model is developed in order to further analyse and extrapolate the source-pull and load-pull measurement results. A good agreement is observed between small signal model simulation results and source-pull/load-pull measurements. Finally, the model is used to evaluate the optimum power gain of the transistor in a circuit configuration under matched conditions.
Modeling and Simulation Graphene based Nano FET : A Review
IRJET, 2023
Graphene-based Field Effect Transistor modelling is described in this article. Utilizing SILVACO TCAD tools, modelling is completed. The structure is built using the virtual ATLAS framework, and the model is used to assess the efficacy of graphene-based FETs. To create the device structure, we first deposit a 5nm thick polysilicon layer rather than a graphene sheet. As the channel material, graphene is used, and it is modelled as a semiconductor with a 10,000 cm 2 /V-s carrier mobility. The output characteristic and transfer curve are plotted as characteristic curves with TONYPLOT. There is no band gap in pure graphene. As a result, it is regarded as a zero bandgap or semi-metal semiconductor. Because GFETs lack a bandgap and have a lower I ON/I OFF ratio than silicon-based transistors, they are still less efficient for use in digital logic circuits than Si transistors. Due to its extreme mobility, it is better suited for RF applications. Thus, in this article, it is possible to get the maximum cutoff frequency (f T) and the maximum oscillation frequency (f max), which are thought to represent the FOMs of RF transistors
IEEE Transactions on Electron Devices, 2011
We present a compact physics-based model of the current-voltage characteristics of graphene field-effect transistors, of especial interest for analog and radio-frequency applications where bandgap engineering of graphene could be not needed. The physical framework is a field-effect model and drift-diffusion carrier transport. Explicit closed-form expressions have been derived for the drain current. The model has been benchmarked with measured prototype devices, demonstrating accuracy and predictive behavior.
Explicit Drain Current, Charge and Capacitance Model of Graphene Field-Effect Transistors
IEEE Transactions on Electron Devices, 2000
I present a compact physics-based model of the drain current, charge and capacitance of graphene field-effect transistors, of relevance for exploration of DC, AC and transient behavior of graphene based circuits. The physical framework is a field-effect model and drift-diffusion carrier transport incorporating saturation velocity effects. First, an explicit model has been derived for the drain current. Using it as a basis, explicit closed-form expressions for the charge and capacitances based on the Ward-Dutton partition scheme, covering continuosly all operation regions. The model is of special interest for analog and radio-frequency applications where bandgap engineering of graphene could be not needed.
Equivalent Circuit Modeling of a Dual-Gate Graphene FET
Electronics, 2020
This paper presents a simple and comprehensive model of a dual-gate graphene field effect transistor (FET). The quantum capacitance and surface potential dependence on the top-gate-to-source voltage were studied for monolayer and bilayer graphene channel by using equivalent circuit modeling. Additionally, the closed-form analytical equations for the drain current and drain-to-source voltage dependence on the drain current were investigated. The distribution of drain current with voltages in three regions (triode, unipolar saturation, and ambipolar) was plotted. The modeling results exhibited better output characteristics, transfer function, and transconductance behavior for GFET compared to FETs. The transconductance estimation as a function of gate voltage for different drain-to-source voltages depicted a proportional relationship; however, with the increase of gate voltage this value tended to decline. In the case of transit frequency response, a decrease in channel length resulte...
Scalable Electrical Compact Modeling for Graphene FET Transistors
IEEE Transactions on Nanotechnology, 2000
A new scalable electrical compact model for the 4 Graphene FET devices is proposed. Starting from Thiele's quasi-5 analytical model, the equations are modified to be now compati-6 ble with SPICE-like circuit simulation. Compared to Meric et al. 7 model, the charge model is improved. This large signal model has 8 been implemented in Verilog-A code and can be used for simula-9 tion in a standard circuit design environment such as Cadence or 10 ADS. This model has been verified using different measurements 11 from the literature, and furthermore, its scalability has also been 12 demonstrated. Q2 13