Microscopic analysis of the impact of substrate bias on the gate current of pMOSFETs (original) (raw)

Thorough characterization of deep-submicron surface and buried channel pMOSFETs

Solid-state Electronics, 2002

In this paper, the short channel effects in buried and surface channel pMOSFETs are studied. The effective channel length, threshold voltage, source-drain series resistance, carrier mobility in various temperature ranges and the draininduced-barrier-lowering effect are investigated. Hot carrier degradation is performed in order to extrapolate the device lifetimes and the maximum drain bias that can be applied. Low frequency noise measurements are also carried out in order to evaluate the impact of the gate doping type on the device noise performance. Ó

Three hot-carrier degradation mechanisms in deep-submicron PMOSFET's

IEEE Transactions on Electron Devices, 1995

Hot-carrier degradation i b niairil) caused by negative oxide-charge generatiou in the present-day PMOSFE'L"5. We present experimental evidence showing that two more degradation mechanisms are importarit in the case of deep-submicron PMOSFET's. Firstly, the geireratiori of interface states is sigiiificant in the case of sub-half-micron PMOSE'EI 's. It even limits the lifetime of surface-channel transistors. Secondly, the generation of positive oxide charge by holes influences the characteristics. The latter process has been established uiiariibiguously for the first time in PMOSFET's.

Accurate modeling of direct tunneling hole current in p-metal-oxide-semiconductor devices

Applied Physics Letters, 2002

We critically examine a number of important issues related to modeling hole direct tunneling in p-metal-oxide-semiconductor devices with p ϩ-polycrystalline silicon gate. By comparing our simulated direct tunneling hole current with experimental data, several observations are made. It is found that inelastic trap scattering of holes in the gate-oxide region increases the hole tunneling current significantly at lower gate voltages in devices with gate-oxide thickness greater than 2 nm. Appropriate spatial and gate bias dependence of the scattering rate needs to be considered for accurately predicting experimental current over the entire gate voltage range. Effective mass of holes in gate-oxide region is not a constant, rather, it increases with increasing gate bias voltage and we propose a relationship between the two. Bulk values for hole effective masses in silicon may be used to accurately model the hole tunneling current even in the presence of hole quantization. The contribution of split-off holes to direct tunneling current is not negligible in strong inversion.

Two-dimensional energy-dependent models for the simulation of substrate current in submicron MOSFET's

IEEE Transactions on Electron Devices, 1994

Two-dimensional energy-dependent substrate current models are described for NMOS and PMOS devices that have been developed using a multi-contour approach. The new models offer a significant improvement in the calculation of substrate current due to a more accurate calculation of the average energy as compared to the local-field model. The models are implemented in a post-processing manner by applying a one-dimensional energy conservation equation to each of many current contours in order to generate a two-dimensional representation of average energy and impact ionization rate, that is then integrated to calculate the substrate current. The new models have been compared to substrate current characteristics of a variety of NMOS and PMOS devices for a wide range of bias conditions and channel lengths, and very good agreement has been obtained with a single set of model parameters. An additional significance of this work is the enhancement of the standard multi-contour model by an energy-sink term that results in an improved prediction of the impact ionization process in PMOSFET's.

New experimental findings on hot carrier effects in deep submicrometer surface channel PMOS

1996

The correlation between gate current and substrate current in surface channel(SC) PMOS with effective channel length down to 0.15/an is investigated within the general framework of the lucky-electron model. It is found that the impact ionization rate increases, but the device degradation is not serious in deep submicrometer PMOS. To extend the lucky-electron model to deep submicrometer regime, we empirically model the effective pinch-off length as a function of the gate length and the gate bias voltage. SCIHE is suggested as the possible physical mechanism for the enhanced impact ionization and the gate current reduction.

A review of gate tunneling current in MOS devices

Microelectronics Reliability, 2006

Gate current in metal-oxide-semiconductor (MOS) devices, caused by carriers tunneling through a classically forbidden energy barrier, is studied in this paper. The physical mechanisms of tunneling in an MOS structure are reviewed, along with the particularities of tunneling in modern MOS transistors, including effects such as direct tunneling, polysilicon depletion, hole tunneling and valence band tunneling and gate current partitioning. The modeling approach to gate current used in several compact MOS models is presented and compared. Also, some of the effects of this gate current in the performance of digital, analog and RF circuits is discussed, and it is shown how new effects and considerations will come into play when designing circuits that use MOSFETs with ultra-thin oxides.

Substrate currents in short buried-channel PMOS devices at cryogenic temperatures

Cryogenics, 1990

For MOSFETs biased in the saturation mode, measurable substrate current due to impact ionization near the drain often flows. If this substrate current is large enough, the substrate bias generator can become overloaded and breakdown can occur if the source-substrate junction is forward biased. Substrate currents can also be used as a reliability monitor of hot carrier effects in short channel MOS devices. In this paper, detailed experimental results are presented on the variation of peak substrate currents in short buried-channel PMOS devices from their IDS-VGS curves at varying substrate and drain biases, at temperatures between 77 and 300 K. From the experimental results, an empirical curve-fit model of the peak substrate current normalized to the drain current and for a constant drain bias was found to be Ip,suB/IDS ~-~x(T, VBs)L ~(T, VBs) Numerical values for the functional dependence of e~ and [3 are determined. Detailed results on these functional dependences on temperature and bias voltages are reported.

Effects of gate bias stressing in power vdmosfets

Serbian Journal of Electrical Engineering, 2003

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analyzed in terms of the mechanisms responsible. In the case of positive bias stressing, electron tunneling from neutral oxide traps associated with trivalent silicon ?Sio defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunneling from the charged oxide traps ?Sio+ to interface-trap precursors ?Sis-H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunneling from the silicon valence band to oxygen vacancy defects ?Sio / Sio? is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors ?Sis?? with the charged oxide traps ?Sio+ Sio? and H+ ions are...

A Semianalytical Description of the Hole Band Structure in Inversion Layers for the Physically Based Modeling of pMOS Transistors

IEEE Transactions on Electron Devices, 2007

This paper presents a new semianalytical model for the energy dispersion of the holes in the inversion layer of pMOS transistors. The wave vector dependence of the energy inside the 2-D subbands is described with an analytical, nonparabolic, and anisotropic expression. The procedure to extract the parameters of the model is transparent and simple, and we have used the band structure obtained with the k • p method to calibrate the model for silicon MOSFETs with different crystal orientations. The model is validated by calculating several transport-related quantities in the inversion layer of a heavily doped pMOSFET and by systematically comparing the results to the corresponding k • p calculations. Finally, we have used the newly developed band-structure model to calculate the effective mobility of pMOS transistors and compare the results with the experimental data. The overall computational complexity of our model is dramatically smaller compared to a fully numerical treatment (such as the k • p method); hence, our approach opens new possibilities for the physically based modeling of pMOS transistors. Index Terms-Crystal orientations, hole mobility, inversion layer, modeling, pMOSFET, valence band structure. I. INTRODUCTION T HE CMOS technology is undergoing a generalized scaling strategy, where the strain engineering [1]-[4], the crystallographic orientation, and the use of alternative channel materials [5]-[11] are being evaluated as possible means to improve the transistor performance. Most of the aforementioned engineering knobs have been suggested on the basis of the experimentally observed mobility enhancements in long-Manuscript