Literature Review on the Power Reduction Techniques and Adders for Approximate Computation (original) (raw)

IJERT-Literature Review on the Power Reduction Techniques and Adders for Approximate Computation

International Journal of Engineering Research and Technology (IJERT), 2013

https://www.ijert.org/literature-review-on-the-power-reduction-techniques-and-adders-for-approximate-computation https://www.ijert.org/research/literature-review-on-the-power-reduction-techniques-and-adders-for-approximate-computation-IJERTV2IS110585.pdf This paper presents literature review on the various techniques involved in attaining power reduction in several computing applications, specifically for digital signal processing. As arithmetic circuits forms the basic functional units in DSP algorithm, the reduction in the complexity of the adder design can bring drastic improvements in the power savings attained. Introduction of designs based on approximate adders provide complexity reduction at transistor level and proved to reduce the switched capacitance, critical path reduction and hence enable voltage scaling provided that low power is attained. Since DSP applications like image compression and video compression are error tolerant, it can be found that even if there are errors in the intermediate outputs it will not form substantial reduction in final output quality.

Quality Improvement and Power Reduction in Digital Signal Processing Using Approximate Adders

Power is an imperative requirement for portable multimedia devices handling different signal processing algorithms and architectures. Human beings can capture useful information even if the output is having some error. Thus, we need not produce exact numerical outputs. Previous researches provide the error resiliency through Voltage Over Scaling (VOS) by various algorithms and architectures to reduce the errors. In this paper, the logic complexity reduction is proposed by using approximate adders which is obtained by reducing the number of transistors without reducing the quality of the output signal. Simulation results shows the power reduction by using approximate adders compared to the actual full adder cells.

Low-Power Digital Signal Processing Using Approximate Adders

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013

Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. We design architectures for video and image compression algorithms using the proposed approximate arithmetic units and evaluate them to demonstrate the efficacy of our approach. We also derive simple mathematical models for error and power consumption of these approximate adders. Furthermore, we demonstrate the utility of these approximate adders in two digital signal processing architectures (discrete cosine transform and finite impulse response filter) with specific quality constraints. Simulation results indicate up to 69% power savings using the proposed approximate adders, when compared to existing implementations using accurate adders.

Design of Optimizing Adders for Low Power Digital Signal Processing

– Low power is the important requirement for portable devices and multimedia devices. Which use several signal processing algorithms and architectures. Previous research uses the error resiliency primarily through voltage over scaling, then using algorithmic and architectural techniques to reduce the resulting errors. In this paper propose logic complexity reduction at the transistor level. This is used as the alternative approach to take advantage of the relaxation of numerical accuracy. We implement this concept by proposing several imprecise or approximate full adder cells with reduced complexity at the transistor level, and these approximate adders are used to design approximate multi-bit adders. In addition to an inherent reduction in switched capacitance as the number of transistor reduces, and which also result in shorter critical paths it also produce voltage scaling Index Terms— Approximate computing, less power, mirror adder.

A Review of Approximate Adders for Energy-Efficient Digital Signal Processing

With the breakdown of Dennard's Scaling the power densities in today's ICs are rapidly reaching unmanageable levels. So there is a need of new sources of efficiency. Approximate computing has emerged as a promising approach to energy-efficient design of digital systems. Approximate computing relies on the ability of many systems and applications to tolerate some loss of quality in the computed result. This loss in quality can be exploited to build circuits with smaller area, lower power and higher performance. The demand of high speed and power as well as the fault tolerance nature of some emerging applications have motivated for the development of approximate adders. Adder plays an important role in determining the speed and power consumption of a digital signal processing (DSP) system. This paper reviews recent progress in the area, and also provides a comparative evaluation in terms of circuit characteristics.

Low Power Digital Image Compression Using Approximate Adders

International Journal for Research in Applied Science & Engineering Technology (IJRASET), 2022

Low power is one of the arising trend in field of VLSI which can be used in multimedia bias employing colorful signal processing algorithms and armature. In utmost multimedia operation mortal beings can gather useful information from incorrect afFull Adderir. Thus we don't need to produce an exact correct numerical afFull Adderir. So we're using different adders to apply this algorithm in signal processing. We design infrastructures for videotape and image contraction algorithms using the proposed approximate computation units and estimate them to demonstrate the efficiency of our approach. We also decide simple fine models for error and power consumption of these approximate adders. The approximate adders are reduced with complexity which are used in designing this algorithm. The proposed adders can achieve significant through afFull Adderir and total power reduction over conventional adders. Simulation results indicate up to 69% power savings using the proposed approximate adders, when compared to being executions using accurate adders.

IMPACT: IMPrecise adders for low-power approximate computing

IEEE/ACM International Symposium on Low Power Electronics and Design, 2011

Low-power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, the final output is interpreted by human senses, which are not perfect. This fact obviates the need to produce exactly correct numerical outputs. Previous research in this context exploits error-resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate Full Adder (FA) cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. We design architectures for video and image compression algorithms using the proposed approximate arithmetic units, and evaluate them to demonstrate the efficacy of our approach. Post-layout simulations indicate power savings of up to 60% and area savings of up to 37% with an insignificant loss in output quality, when compared to existing implementations.

Design Of Low Power Approximate Mirror Adder

Addition is a fundamental operation for any digital system, digital signal processing and control system. A quick and accurate operation of a digital system is greatly influenced by the performance of the resident adders. Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most of the multimedia applications human beings can gather useful information from slightly erroneous outputs. Therefore, we cannot need to produce exactly correct numerical outputs. Preceding research in this context exploits error resiliency primarily through voltage over scaling, make use of algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic difficulty reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this idea by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and make use of them to design approximate multibit adders. In addition to the inherent decrease in switched capacitance, our techniques result in significantly smaller difficult paths, enabling voltage scaling. We design architectures for video and image compression algorithms using the proposed approximate arithmetic units and evaluate them to demonstrate the efficacy of our approach. We also derive clear mathematical models for error and power consumption of these approximate adders. Index Terms: Approximate Mirror Adder, low power

A Study of Approximate Arithmetic Circuit Designs for Digital Signal Processing Systems

Approximate computing has gained significant attention as a promising strategy for digital signal and image processing applications. This article reviews the relevant research aimed at development of approximate arithmetic circuits and provides an overview of their performance in digital signal processing systems. The incessantly growing demand for compactness and speed in portable multimedia devices and embedded systems, continues to drive the need for novel approximation techniques. This review research paper is aimed at serving as a guideline for further research on inexact computing.