Literature Review on the Power Reduction Techniques and Adders for Approximate Computation (original) (raw)

This paper presents literature review on the various techniques involved in attaining power reduction in several computing applications, specifically for digital signal processing. As arithmetic circuits forms the basic functional units in DSP algorithm, the reduction in the complexity of the adder design can bring drastic improvements in the power savings attained. Introduction of designs based on approximate adders provide complexity reduction at transistor level and proved to reduce the switched capacitance, critical path reduction and hence enable voltage scaling provided that low power is attained. Since DSP applications like image compression and video compression are error tolerant, it can be found that even if there are errors in the intermediate outputs it will not form substantial reduction in final output quality.