Precise DRAM Energy Modeling (original) (raw)
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MeSAP: A fast analytic power model for DRAM memories
2017
The design of an energy-efficient memory subsystem is one of the key issues that system architects face today. To achieve this goal, architects usually rely on system simulators and trace-based DRAM power models. However, their long execution time makes the approach infeasible for the design-space exploration of next-generation exascale computing systems. Analytic models, in contrast, are orders of magnitude faster. In this paper, we propose a new analytic memory-scheduler-agnostic power model for DRAM, henceforth referred to as MeSAP. Similarly to state-of-the-art trace-based approaches, our analytic model achieves an average error of 20%, while being an order of magnitude faster. Furthermore, we integrate MeSAP into an analytic performance model of general-purpose processors and show its applicability to the design of a computing system targeting scientific image processing applications.
A comprehensive approach to DRAM power management
2008 IEEE 14th International Symposium on High Performance Computer Architecture, 2008
This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power. We make three contributions: (1) we describe a simple power-down policy for exploiting low power modes of modern DRAMs; (2) we show how the idea of adaptive history-based memory schedulers can be naturally extended to manage power and energy; and (3) for situations in which additional DRAM power reduction is needed, we present a throttling approach that arbitrarily reduces DRAM activity by delaying the issuance of memory commands. Using detailed microarchitectural simulators of the IBM Power5+ and a DDR2-533 SDRAM, we show that our first two techniques combine to increase DRAM energy efficiency by an average of 18.2%, 21.7%, 46.1%, and 37.1% for the Stream, NAS, SPEC2006fp, and commercial benchmarks, respectively. We also show that our throttling approach provides performance that is within 4.4% of an idealized oracular approach.
Developing dynamic power management strategies for high performance systems requires a good understanding of the power-performance trade-offs underlining the workload-strategy-system interactions. The feasibility of detailed simulations to help here is severely limited by the range of problem sizes that can be simulated and simulation speed. For our work we want to understand the effectiveness of DRAM power management for a 'realistic' workload-RF-CTH-about 500K lines of Fortran-C benchmark developed at Sandia National Labs. The target architecture is a CMP-based building block for a future high performance computing architecture. We address the scalability and speed limitations for detailed simulation by adopting a multistep characterization and simulation approach incorporating analysis on current generation hardware using processor performance counters, a fast memory hierarchy simulation engine, a detailed system-level simulator and a power-performance simulator for the DRAM subsystem.
2004
AbstractWe present a model for estimating the power consumption of SDRAM at an architectural level. The approach is based on identifying the various operating states for a typical SDRAM, and using the knowledge of current drawn by the memory chip, and fraction of ...
Review of Energy Saving Strategies for DRAM
The ever increasing power consumption of the components within a computing system have resulted in tremendous costs and substantial failure rates which are a roadblock in achieving optimal performance at reasonable costs. To mitigate these issues, strategies that reduce the dynamic power consumption of these components are needed. In this paper, we review a survey a subset of those strategies with their salient features and their efficacy in providing energy savings. The paper reviews energy saving strategies proposed and verified in both simulators and real-time systems.
In current scenario while designing a computing system it is necessary that detailed emphasis should be laid on two common goals, i.e., increasing performance and decreasing power consumption. As we needto achieve either more performance at same power level or minimum power consumption for same performance level. Main memory of a system is one of the key resources that a program needs to run hence it acts as a major contributor towards both system's performance and power consumption. Main memory's performance depends on the way it accesses its contents. It is memory controller's access scheduler that decides which command to issue in every DRAM clock cycle on the basis of employed memory access scheduling policy. Based on underlying access strategy DRAM operations are scheduled in a way that it reduces DRAM's latency and power consumption by utilizing low power modes. In this paper, we have compared and analysedvarious memory access scheduling algorithms on the basis ofpage hit rate, energy-delay product, total execution time and maximum slowdown time.This analysis contributes to better understand how the performance and energy consumption of DRAM memory system is affected by the underlying memory controller's scheduling policies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015
Framework is developed for estimation of power at pre register transfer level (RTL) stage for structured memory subsystems. Power estimation model is proposed specifically targeting power consumed by clock network and interconnect. The model is validated with VCD-based simulation on back-annotated netlist of an 8 MB memory subsystem used as video RAM (VRAM) for high-end graphics applications. This methodology also forms the basis for low-power exploration driving floor plan choice, gating structure of data, and clock network. We demonstrate 57% reduction in dynamic power by using low-power techniques for the 8 MB VRAM used as frame buffer in a graphics processor. FALPEM can be extended to other applications like processor cache and ASIC designs.
An Approach for Adaptive DRAM Temperature and Power Management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010
With rising capacities and higher accessing frequencies, highperformance DRAMs are providing increasing memory access bandwidth to the processors. However, the increasing DRAM performance comes with the price of higher power consumption and temperature in DRAM chips. Traditional low power approaches for DRAM systems focus on utilizing low power modes, which is not always suitable for high performance systems. Existing DRAM temperature management techniques, on the other hand, utilize generic temperature management methods inherited from those applied on processor cores. These methods reduce DRAM temperature by controlling the number of DRAM accesses, similar to throttling the processor core, which incurs significant performance penalty. In this paper, we propose a customized low power technique for high performance DRAM systems, namely the Page Hit Aware Write Buffer (PHA-WB). The PHA-WB improves DRAM page hit rate by buffering write operations that may incur page misses. This approach reduces DRAM system power consumption and temperature without any performance penalty. Our proposed Throughput-Aware PHA-WB (TAP) dynamically configures the write buffer for different applications and workloads, thus achieves the best trade off between DRAM power reduction and buffer power overhead. Our experiments show that a system with TAP could reduce the total DRAM power consumption by up to 18.36% (8.64% on average). The steady-state temperature can be reduced by as much as 5.10°C and by 1.93°C on average across eight representative workloads.
Reducing SDRAM Energy Consumption in Embedded Systems
2000
DRAM energy consumption in embedded systems can be very high, exceeding that of the data cache or even of the entire processor. This paper presents a scheme for reducing the energy consumption of SDRAM memory access by a combination of techniques that take advantage of SDRAM energy efficiencies in bank and row access. This is achieved by using small, cachelike structures in the memory controller to prefetch an additional cache block(s) on reads and to combine block writes to the same DRAM row. The results quantify the DRAM energy consumption of MiBench applications and demonstrate significant savings in both the DRAM energy consumption, an average of 23%, and the energy-delay product, an average of 44%. The approach also improves performance: the CPI is reduced by 26% on an average.
ACM Transactions on Design Automation of Electronic Systems, 2008
Memory devices often consume more energy than microprocessors in current portable embedded systems, but their energy consumption changes significantly with the type of transaction, data values, and access timing, as well as depending on the total number of transactions. These variabilities mean that an innovative tool and framework are required to characterize modern memory devices running in embedded system architectures. We introduce an energy measurement and characterization platform for memory devices, and demonstrate an application to multilevel-cell (MLC) flash memories, in which we discover significant value-dependent programming energy variations. We introduce an energy-aware data compression method that minimizes the flash programming energy, rather than the size of the compressed data, which is formulated as an entropy coding with unequal bit-pattern costs. Deploying a probabilistic approach, we derive energy-optimal bit-pattern probabilities and expected values of the bit...