USE OF FEEDFORWARD AND FEEDBACK IN OVERSAMPLED ANALOG TO DIGITAL CONVERTERS TO BYPASS PERFORKANCE CONSTRAINTS RELATED TO ANALOG CIRCUIT COMPONENTS (original) (raw)
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Use of Feedforward and Feedback in Oversampled Analog to Digital Converters to Bypass Performance Co
1990 Conference Record Twenty-Fourth Asilomar Conference on Signals, Systems and Computers, 1990.
system performance of an oversampled Analog to Digital Converter (ADC) with feedback noise shaping is limited by the precision of the Digital to Analog Converter (DAC) in the feedback path as well as by the number of integrators in the loop(s). The integrators in the feedback loop of the quantizer are the source of the transmission zeros which suppress the in-band quantizing noise. The design bandwidth, defined as the fraction of the sample rate for which the noise level is sufficiently suppressed, increases with the order of the Yoop. Standard designs avoid the DAC precision problem by restricting the ADC and DAC to a single bit while stability and matching considerations limit systems to three loops. This in turn defines the oversample ratio for a given effective tandwidth and noise performance. We present simple modifications to the oversampled ADC which avoids these limitations via local feedback in the feedback path and local feedforward in the feedforward path of the original delta sigma loop structure. These modifications result in wider conversion bandwidth and greater dynamic range than is available from standard configurations.
Improved performance of multi-bit delta-sigma analog to digital converters via requantization
1991., IEEE International Sympoisum on Circuits and Systems
System performance of an oversampled analog to digital converter (ADC) with feedback noise shaping is limited by the precision of the digital to analog converter (DAC) in the feedback path as well as by the number of integrators in the loop(s): Standard designs avoid the DAC precision problem by restricting the ADC and DAC to a single bit while stability and matching considerations limit systems to three loops. This limit in turn defines the oversample ratio for a given effective bandwidth and noise performance. We present a simple modification to the oversampled ADC which avoids these limitations via requantization in the feedback path of the original delta sigma loop structure. This modification results in greater dynamic range than is available from standard configurations.
International Conference on Acoustics, Speech, and Signal Processing
A major factor limiting the performance of many DSP based systems is the resolution of the analog to digital converter (ADC). We encounter this limitation, for instance, in systems simultaneouslyhandlinglowleveland high level signals such as a communication system operating in the presence of strong interference. We and others have reported a number of techniques for improving the accuracy and the dynamic range of ADCs by operating a reduced resolution quantizer in a feedback loop. These techniques are seen to be special cases of noise feedback coding in which the loop operates at sample rates far in excess of the signal bandwidth and uses spectral noise shaping to shift in-band quantizing noise power to out-of-band spectral positions. Implementing these techniques at very high sample rates (10' samples per second) with combinations of analog and digital subsystems offer a number of challenging signal processing problems. We present an overview of these techniques, then identify important design issues and limitations as well a6 verify expected ADC dynamic range performance. DTRODUCTION
Delta-sigma algorithmic analog-to-digital conversion
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2002
Delta-sigma modulation for analog-to-digital conversion resolves a number of bits logarithmic in the number of modulation cycles, and linear in modulation order. As an alternative to higher-order noise shaping, we present an algorithmic scheme that iteratively resamples the modulation residue, by feeding the integrator output back to the input. This yields a bit resolution linear in the number of cycles, similar to an algorithmic analog-to-digital converter. The scheme simplifies the design of the digital decimator to a single shifting counter, and avoids interstage gain errors in conventional algorithmic analog-to-digital converters. Experimental results from an integrated CMOS array of 128 converters show the utility of the design for large-scale parallel quantization in digital imaging and hybrid analogdigital computing. § © incremental converter [2], where a counter implements a rectangular decimation filter. Higher-order § © § © incremental A/D converter. (b) §
Novel loop architectures for enhancing linearity and resolution of analog-to-digital converters
Analog Integrated Circuits and Signal Processing, 2010
This paper proposes three mixed (analog and digital) loop architectures which involve an analog-to-digital converter and enhance its linearity and its resolution. Their benefits are discussed with mathematical models and high-level simulations (the ADC inserted in the loops is then a passive sigma-delta structure). One of the loop topologies is particularly highlighted: it is ideally able to enhance resolution by 5 bits without damaging bandwidth. The only added analog element is an active differential low-pass filter. The other operators are fully digital: a predictor and some models of the analog parts. The effect of some defaults, such as mismatch and common mode, is illustrated by high-level simulations. The needed accuracy for the digital parameters is evaluated to 16 bits. The test of a prototype realized in a 0.35µm CMOS technology validates the principle and demonstrates that the critical element of the structure is the active differential filter.
An Overview of Sigma-Delta Converters: How a 1-bit ADC achieves more than 16-bit resolution
Departmental Papers, 1996
This article briefly describes conventional A/D conversion, as well as its performance modeling. We then look at the technique of oversampling, which can be used to improve the resolution of classical A/D methods. We discuss how sigma-delta converters use the technique of noise shaping in addition to oversampling to allow high resolution conversion of relatively low bandwidth signals. Next, we examine the use of sigma-delta converters to convert narrowband bandpass signals with high resolution. Several parallel sigma-delta converters, which offer the potential of extending high resolution conversion to signals with higher bandwidths, are also described.
A 13 bit ISDNband Oversampled ADC using TwoStage Third Order Noise Shaping
Oversampling Delta-Sigma Data Converters, 1991
A 13 bit 80kHz baseband analog-to-digital converter suitable for use in applications such as the ISDN 'U'-interface will be described. Two-stage third order noise shaping permits the use of a sampling frequency of only 2.56MHz. The circuit has been implemented using conventional single-ended switched-capacitor techniques in a 1. 5~ CMOS process.
Enhancing Analog to Digital Converter Resolution Using Oversampling Technique
This paper is going to expose a method that gives us the possibility to use a low-resolution Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) in high resolution measurements. Oversampling and averaging can increase the resolution of a measurement without resorting to the cost and complexity of using expensive off-chip ADC's. This paper discusses about oversampling method for increase the resolution of a 12-bits ADC to 16-bits ADC. Oversampling method also rejects the noise by using averaging or moving averaging method. Oversampling method provides a softwarebased technique, resulting in an improved effective number of bits (ENOB) in the conversion result. It can be only used for measuring very low frequency or continuous signals, but the costs are lower compared to the price of the same highresolution converter. This paper discusses how to increase the resolution of ADC measurements by oversampling and averaging. Additionally, more in-depth description on types of ADC, theory of oversampling technique and example code on utilizing oversampling and averaging.
A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio
IEEE Journal of Solid-State Circuits, 2005
An audio 61 analog-to-digital converter (ADC) with the loop filter implemented by continuous-time (CT) and discretetime (DT) circuits is presented. A tuning circuit is used to compensate for changes in the RC product due to process skew, power supply, temperature and sampling rate variation. To eliminate errors caused by inter-symbol interference (ISI) in the CT feedback DAC, a return-to-zero (RTZ) switching scheme is applied on the error current of the CT integrator. The converter is fabricated in a 0.35-m CMOS process, and achieves 106-dB dynamic range, 99-dB THD +. Index Terms-Continuous time 61 modulator, oversampling ADC.