A novel bidirectional CMOS transceiver for chip-to-chip optical interconnects (original) (raw)
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Bidirectional CMOS Transceiver With Automatic Mode Control for Chip-to-Chip Optical Interconnects
IEEE Photonics Technology Letters, 2009
A bidirectional transceiver (Bi-TRx) integrated with a novel transmission envelope detector, which can detect the presence of received signals to generate a mode control signal automatically, is proposed in this letter. Implemented in a 0.18-m complementary metal-oxide-semiconductor technology, the Bi-TRx occupies an area of 1.08 mm 2 , and dissipates 42 and 49 mW in transmitter (Tx) and receiver (Rx) modes, respectively. It achieves a 3-dB bandwidth of 4.4 and 4 GHz in Tx and Rx modes, respectively, while the disabled outputs for the Tx and Rx modes are isolated with 41 and 68 dB, respectively, from the enabled outputs.
Power saving bidirectional optical transceiver design and fabrication
Optical and Quantum Electronics, 2015
In this paper, a bidirectional optical transceiver module has been proposed. The module is designed such as way to have the capability to save power. The proposed transceiver for chip-to-chip optical interconnect is designed and fabricated using a 130 nm CMOS technology. The transceiver saves up to 55 and 35 % power in receiver (Rx) enabled and transmitter (Tx) enabled modes, respectively. The area of the fabricated chip is 0.97 9 0.78 mm 2. We investigated the fabricated module performance by 10 Gb/s data rate and measured bit error rate less than 10-12 with-12 and-13 dBm received optical power at Tx and Rx, respectively. The clear eye-diagrams were observed at 10 Gb/s data rate with minimum input power of-13 dBm at the Rx.
2007 Proceedings 57th Electronic Components and Technology Conference, 2007
We report here on the design, fabrication and high-speed performance of a novel parallel optical module with sixteen 10-Gb/s transmitter and receiver channels for a 160-Gb/s bidirectional aggregate data rate. The module utilizes a single-chip CMOS optical transceiver containing both transmitter and receiver circuits. 16-channel high-speed photodiode (PD) and VCSEL arrays are flip-chip attached to the low-power CMOS IC. The substrate emitting/illuminated VCSEL and PD arrays operate at 985 nm and include collimating lenses integrated into the backside of the substrate. The IC-OE assembly is then flip-chip attached to a high density organic package forming the transceiver optical module. The exclusive use of flip-chip packaging for both the IC-to-optoelectronic (OE) devices and for the IC-toorganic package minimizes the module footprint and associated packaging parasitics. The OE-on-IC assembly achieves a high area efficiency of 9.4 Gb/s/mm 2 [1]. The complete organic carrier transceiver package provides a lowcost, low-profile module similar to a conventional chip-carrier that can be directly surface mounted to a circuit board using a conventional BGA solder process. SLC transceiver modules with transmitter and receiver OE-IC arrays were assembled and characterized. Operation of all 16 transmitters in the transceiver module was demonstrated at data rates >10 Gb/s. Similarly, all 16 receiver channels operated error-free at >10 Gb/s. The receiver eye-diagrams were generated using a second transceiver source and therefore constitute a full transceiver optical link.
Optical I/O for Chip-to-Chip Interconnects on CMOS Platform
Optical Fiber Communication Conference/National Fiber Optic Engineers Conference 2011, 2011
Optical devices on a CMOS die and package for terabit computing are discussed. 200Gbps transmission is accomplished with a 1x10 VCSEL array. CMOS backend compatible modulators and photodetectors are demonstrated at 40Gbps for on-die integration.
A Sub-pJ/Bit, Low-ER Mach–Zehnder-Based Transmitter for Chip-to-Chip Optical Interconnects
IEEE Journal of Selected Topics in Quantum Electronics, 2020
Designing high-speed and low-power interconnects is a challenge for high performance computing applications, while silicon photonics can provide attractive solutions to perform high-density communications. This paper presents an electrooptic transmitter operating at 20 Gbps (gigabit per second), as a first step toward the demonstration of chip-to-chip optical links. The architecture is based on a dual-drive Mach-Zehnder interferometer co-integrated with a 55-nm CMOS driver. Design optimizations and trade-offs analysis enable low-energy and negligible bit error rate (BER < 10 −12) transmission at 20 Gbps, by exploring a firstly reported low extinction ratio (ER) modulator. A wire-bonding board assembly is then carried out to co-integrate hybrid transmitter. Co-simulations are presented and show good agreement with experiments. Combined with an adequate MZM bias, this solution achieves a minimal energy consumption of 0.9 pJ/bit while ensuring a sufficiently large ER of 0.73 dB for chip-to-chip interconnects applications. Index Terms-Silicon photonics, chip-to-chip communication, hybrid integration, co-simulation, Mach-Zehnder modulator I. INTRODUCTION S ILICON photonics (SiP) is considered as a prime technology for high performance computing (HPC) applications [1], [2]. Indeed, future supercomputer architectures require high-speed and high-capacity data transmission solutions, but traditionally used metal interconnects suffer from relevant crosstalk and bandwidth limitations. Optical technologies are therefore emerging as attractive solutions for short range communications, and are suitable, for instance, to connect the cores (CPU/GPU) and the multiple memory resources of a supercomputer. Moreover, silicon photonics has the potential for large-scale industrialization, thus addressing the cost, size, and energy challenges of optical interconnects. Such advance is already proved in the electronic-photonic system proposed by C. Sun et al. in 2015, where over 70 million transistors and 850 photonic components are integrated on a single chip to provide logic, memory, and interconnect functions [3]. Very low distance chip-to-chip links are of growing research interest, but few papers demonstrate a complete proof of The authors would like to thank Philippe Grosse with CEA LETI for many useful discussions and for his assistance in the measurement. They also thank Laura Boutafa with CEA LETI for enabling the board assembly. The authors are grateful to David Fowler for his thorough proofreading.
SPIE Proceedings, 2008
We describe the design and development of a high-speed 8-channel hybrid integrated optical transceiver package with Clock and Data Recovery (CDR) circuits. The package concept has been developed to be compatible with microprocessor package technology and at the same time allow the integration of low cost, high-performance optical components. A 90nm CMOS optical transceiver chip, 850nm 10Gb/s GaAs based vertical cavity surface emitting laser (VCSEL) array and PIN photodiode array are flip-chip mounted on a standard microprocessor Land Grid Array (LGA) package substrate. The CMOS drivers and receivers on the transceiver chip and the optical components (VCSEL and Photodiode arrays) are electrically coupled using a short transmission line routed on the top surface of the package. VCSEL and photodiode arrays are optically coupled to on-package integrated polymer waveguide arrays with metallized 45 o mirrors. The waveguides, which are terminated with multi-terminal (MT) fiber optic connectors, couple out/in highspeed optical signals to/from the chip. The CMOS transceiver chip fully integrates all analog optical circuits such as VCSEL drivers, transimpedance amplifiers and clock and data recovery (CDR) retiming circuit with a low jitter LC-PLL. Digital circuits for pseudorandom bit-pattern sequence generators (PRBS) and bit-error rate test (BERT) are fully integrated. 20Gb/s electrical and 18Gb/s optical eye diagrams for the transmitter were measured out of the package. A fully packaged transmitter and receiver including clock data recovery at 10Gb/s have also been measured.
Stacked silicon CMOS circuits with a 40-Mb/s through-silicon optical interconnect
IEEE Photonics Technology Letters, 2000
Optical interconnection through stacked silicon foundry complementary metal-oxide-semiconductor (CMOS) circuitry has been demonstrated at a data rate of over 40 Mb/s with an open eye diagram. The system consists of a 0.8-m transmitter and receiver realized in foundry digital CMOS. The use of digital CMOS enables on-chip integration with more complex digital systems, such as a microprocessor. Two layers of these circuits were integrated with thin-film InP-based light emitting diodes and metal-semiconductor-metal photodetectors operating at 1.3 m (to which the silicon is transparent) to enable vertical optical through-Si communication between the stacked silicon circuits.
Applied Optics, 2006
A 2 Gb͞s 0.5 m complementary metal-oxide semiconductor optical transceiver designed for board-or backplane level power-efficient interconnections is presented. The transceiver supports optical wake-onlink (OWL), an event-driven dynamic power-on technique. Depending on external events, the transceiver resides in either the active mode or the sleep mode and switches accordingly. The active-to-sleep transition shuts off the normal, gigabit link and turns on dedicated circuits to establish a low-power ͑ϳ1.8 mW͒, low data rate (less than 100 Mbits͞s) link. In contrast the normal, gigabit link consumes over 100 mW. Similarly the sleep-to-active transition shuts off the low-power link and turns on the normal, gigabit link. The low-power link, sharing the same optical channel with the normal, gigabit link, is used to achieve transmitter͞receiver pair power-on synchronization and greatly reduces the power consumption of the transceiver. A free-space optical platform was built to evaluate the transceiver performance. The experiment successfully demonstrated the event-driven dynamic power-on operation. To our knowledge, this is the first time a dynamic power-on scheme has been implemented for optical interconnects. The areas of the circuits that implement the low-power link are approximately one-tenth of the areas of the gigabit link circuits.
Two-dimensional optical interconnect between CMOS IC's
2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)
The central issue of optically interconnected integrated circuits (OIIC) concerns the area optical interconnect approach to the interconnect bottleneck encountered in advanced VLSI-CMOS designs. The envisaged route to solving this problem offers throughput data interconnects on inter-chip and MCM level, facilitating implementation of new digital architectures and systems. The OIIC project is aimed towards the realisation of three demonstrators: a