Designing Efficient Imprecise Adders using Multi-bit Approximate Building Blocks (original) (raw)
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IMPACT: IMPrecise adders for low-power approximate computing
IEEE/ACM International Symposium on Low Power Electronics and Design, 2011
Low-power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, the final output is interpreted by human senses, which are not perfect. This fact obviates the need to produce exactly correct numerical outputs. Previous research in this context exploits error-resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate Full Adder (FA) cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. We design architectures for video and image compression algorithms using the proposed approximate arithmetic units, and evaluate them to demonstrate the efficacy of our approach. Post-layout simulations indicate power savings of up to 60% and area savings of up to 37% with an insignificant loss in output quality, when compared to existing implementations.
DrAx: An Automatic Approach to Designing More Precise and Energy-Efficient Approximate Adders
As Moore's Law scaling tapers off, there is a growing emphasis on improving the energy-efficiency of nanometer ICs through architectural techniques. Recently, approximate computing has been introduced to address the energy-efficiency problems of error-tolerant applications in all forms of computing from mobile IoT devices to data centers and servers. This technique has proved successful in various application domains such as digital signal processing, deep machine learning, and combinatorial optimization. Approximate computing trades accuracy for power, delay, and area in computing systems. One key arithmetic circuit in digital signal processing is the multi-bit digital adder that is widely used in today's user applications. Adders consume significant amounts of system energy and occupy large portions of the processor die area. The need for low power and high-speed circuits as well as the error-resiliency of the digital signal processing systems allow the system designers to innovate energy-efficient approximate adders. This paper examines DrAx, a design remedy for approximation, which provides an automatic method to improve the accuracy of approximate adders with virtually no impact on their power and area consumption. The proposed method is applied to seven state-of-the-art approximate adders for evaluation; our simulation results indicate 12-50% accuracy regarding mean error distance metric improvements are attainable for the baseline approximate adders using the proposed design approach.
A Review of Approximate Adders for Energy-Efficient Digital Signal Processing
With the breakdown of Dennard's Scaling the power densities in today's ICs are rapidly reaching unmanageable levels. So there is a need of new sources of efficiency. Approximate computing has emerged as a promising approach to energy-efficient design of digital systems. Approximate computing relies on the ability of many systems and applications to tolerate some loss of quality in the computed result. This loss in quality can be exploited to build circuits with smaller area, lower power and higher performance. The demand of high speed and power as well as the fault tolerance nature of some emerging applications have motivated for the development of approximate adders. Adder plays an important role in determining the speed and power consumption of a digital signal processing (DSP) system. This paper reviews recent progress in the area, and also provides a comparative evaluation in terms of circuit characteristics.
IDrAx: A tool-chain for designing efficient approximate adders
Microelectronics Journal, 2019
As transistors shrink down, improving the energy-efficiency of nanometer ICs has gained a great deal of attention. Recently, approximate computing has been introduced to address energy-efficiency problems of error-tolerant systems. Adders are the most widely used arithmetic modules that consume significant amounts of system's total energy and area. The error-resiliency of these systems has made it possible to innovate energy-efficiency approximate adders to obtain low power and high-speed circuits. This paper presents IDrAx, an approach to improve the accuracy of approximate adders. The goal is to find the most significant errors in the error distribution for the given circuit and correct them through low-cost additional circuits. The proposed method is applied to several state-of-the-art approximate adders for evaluation by considering two different input distributions. Our simulation results indicate that the proposed design achieves by 75% and 78.01% accuracy regarding mean error distance metric for uniform and normal input distributions, respectively.
Low-Power Digital Signal Processing Using Approximate Adders
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013
Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. We design architectures for video and image compression algorithms using the proposed approximate arithmetic units and evaluate them to demonstrate the efficacy of our approach. We also derive simple mathematical models for error and power consumption of these approximate adders. Furthermore, we demonstrate the utility of these approximate adders in two digital signal processing architectures (discrete cosine transform and finite impulse response filter) with specific quality constraints. Simulation results indicate up to 69% power savings using the proposed approximate adders, when compared to existing implementations using accurate adders.
2017 IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies (AEECT)
Approximate computing has recently introduced a new era of low-power and high-speed circuit designs. Recent efforts in the domain of configurable-accuracy approximate designs have proposed substantial performance gains and energy savings by allowing performance-energy-accuracy trade-offs. In this paper, we propose a configurable-accuracy approximate adder with new lightweight error detection technique. This is followed by significance-driven error correction stages during run-time. The correction starts by recovering the higher magnitude errors at premier correction stages, which results in fast convergence and higher precision outputs. Compared to other equivalent approximate adders, the proposed design has drastically reduced the logic counts used for error detection process; hence, achieving lower overhead of silicon area and improving the energy-efficiency of the adder design with faster convergence to the exact results. A number of different bitwidths of the proposed adder (32-bit to 256-bit) are designed in Verilog and synthesized using Synopsys Design Compiler. Our post-synthesis experiments showed significant reductions of 12% and 10% for Dynamic and Leakage Power respectively, and 8% in the silicon area for the design with full correction stages. Moreover, the proposed adder with large bit-widths has reserved these reduction ratios while presenting better scalability overhead. Additionally, our low overhead proposed design has presented the chance to be improved in terms of increasing accuracy to reach 100% exact results as accurate conventional adder at the final correction stage.
High Performance and Optimal Configuration of Accurate Heterogeneous Block-Based Approximate Adder
ArXiv, 2021
Approximate computing is an emerging paradigm to improve power and performance efficiency for error-resilient application. Recent approximate adders have significantly extended the design space of accuracy-power configurable approximate adders, and find optimal designs by exploring the design space. In this paper, a new energy-efficient heterogeneous block-based approximate adder (HBBA) is proposed; which is a generic/configurable model that can be transformed to a particular adder by defining some configurations. An HBBA, in general, is composed of heterogeneous sub-adders, where each sub-adder can have a different configuration. A set of configurations of all the sub-adders in an HBBA defines its configuration. The block-based adders are approximated through inexact logic configuration and truncated carry chains. HBBA increases design space providing additional design points that fall on the Pareto-front and offer better power-accuracy tradeoff compared to other configurations. Fu...
Approximate single precision floating point adder for low power applications
With an increasing demand for power-hungry data-intensive computing, design methodologies with low power consumption are increasingly gaining prominence in the industry. Most of the systems operate on critical and noncritical data both. An attempt to generate a precision result results in excessive power consumption and results in a slower system. For noncritical data, approximate computing circuits significantly reduce the circuit complexity and hence power consumption. In this paper, a novel approximate single precision floating point adder is proposed with an approximate mantissa adder. The mantissa adder is designed with three 8-bit full adder blocks. In this paper, a detailed mathematical background, and proposed design approach in terms of the circuit configuration and truth tables are discussed. Additionally, a concept of switching between exact computing and approximate computing is analysed considering an approximate carry look-ahead adder. The delay and power consumption for the exact operating mode and approximate operation mode considering varied window sizes is observed. Performance of the approximate computation is compared against exact computation and varied approximate computing approaches.
Hybrid approximate multiplier architectures for improved power-accuracy trade-offs
2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2015
Approximate computing forms a promising design alternative for inherently error resilient applications, trading accuracy for power savings. In this paper, we exploit multi-level approximation, i.e. at the algorithmic, the logic and the circuit level, to design low power approximate arithmetic architectures for hardware multipliers. Motivated from the limited power savings that approximation techniques can achieve in isolation, we explore hybrid methods that apply simultaneously more than one techniques from different layers. We introduce the concept of perforation for approximate arithmetic circuit design and we explore the newly defined design space of hybrid designs showing that it leads to lower power consumption at every examined error range. To address the increased complexity of the target design space, we introduce an heuristic optimization technique and the corresponding design framework that automatically generates hybrid low-power approximate multipliers requiring a small number of design evaluations, i.e. synthesis, simulation, power and timing analysis. Through extensive experimentation, we show that the proposed techniques converge towards optimal solutions and deliver approximate designs that are always more efficient with respect to state-of-art approaches. Power savings of 11% are reported for small error bounds and more than 30% in case of more relaxed error constraints.
Energy-efficient approximate multiplier design using bit significance-driven logic compression
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017
Approximate arithmetic has recently emerged as a promising paradigm for many imprecision-tolerant applications. It can offer substantial reductions in circuit complexity, delay and energy consumption by relaxing accuracy requirements. In this paper, we propose a novel energy-efficient approximate multiplier design using a significance-driven logic compression (SDLC) approach. Fundamental to this approach is an algorithmic and configurable lossy compression of the partial product rows based on their progressive bit significance. This is followed by the commutative remapping of the resulting product terms to reduce the number of product rows. As such, the complexity of the multiplier in terms of logic cell counts and lengths of critical paths is drastically reduced. A number of multipliers with different bit-widths (4-bit to 128-bit) are designed in SystemVerilog and synthesized using Synopsys Design Compiler. Post-synthesis experiments showed that up to an order of magnitude energy savings, and reductions of 65% in critical delay and almost 45% in silicon area can be achieved for a 128-bit multiplier compared to an accurate equivalent. These gains are achieved with low accuracy losses estimated at less than 0.00071 mean relative error. Additionally, we demonstrate the energy-accuracy trade-offs for different degrees of compression, achieved through configurable logic clustering. In evaluating the effectiveness of our approach, a case study image processing application showed up to 68.3% energy reduction with negligible losses in image quality expressed as peak signal-to-noise ratio (PSNR).