Non-Overlapped Single/Double Gate SOI/GOI MOSFET for Enhanced Short Channel Immunity (original) (raw)
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2008
In the present work a methodology to minimize short channel effects (SCEs) by modulating the effective channel length is proposed to design 25 nm single and double gate-source/drain underlap MOSFETs. The analysis is based on the evaluation of the ratio of effective channel length to natural/ characteristic length. Our results show that for this ratio to be greater than 2, steeper source/drain doping gradients along with wider source/drain rolloff widths will be required for both devices. In order to enhance short channel immunity, the ratio of source/drain roll-off width to lateral straggle should be greater than 2 for a wide range of source/drain doping gradients.
Analytical study of Dual Material Surrounding Gate MOSFET to suppress short-channel effects (SCEs)
Engineering Science and Technology, an International Journal, 2014
In this paper, a 2D analytical model for the Dual Material Surrounding Gate MOSFET (DMSG) by solving the Poisson equation has been proposed and verified using ATLAS TCAD device simulator. Analytical modeling of parameters like threshold voltage, surface potential and Electric field distribution is developed using parabolic approximation method. A comparative study of the SCEs for DMSG and SMSG device structures of same dimensions has been carried out. Result reveals that DMSG MOSFET provides higher efficacy to prevent short-channel effects (SCEs) as compared to a conventional SMSG MOSFET due to the presence of the perceivable step in the surface potential profile which effectively screen the drain potential variation in the source side of the channel. A nice agreement between the results obtained from the model and the results obtained from numerical TCAD device simulator provides the validity and correctness of the developed model.
Journal of Engineering, 2013
In this paper a comprehensive investigation of a novel device called split-gate silicon-on-insulator MOSFET (SPG SOI MOSFET) is proposed to reduce short-channel effects (SCEs). Studying the device has been done by analytical approach and simulation. In the proposed structure the gate is split into two parts. A voltage difference exists between the two parts. It is demonstrated that the surface potential in the channel region exhibits a step function. Some improvements are obtained on parameters such as SCEs, hot-carrier effect (HCE), and drain-induced barrier lowering (DIBL). The accuracy of the results obtained by use of the analytical model is verified by ATLAS device simulation software. The obtained results of the model are compared with those of the single-gate (SG) SOI MOSFET. The simulation results show that the SPG SOI MOSFET performance is superior.
Comparison of electrical characteristics between Bulk MOSFET and Silicon-on-insulator (SOI) MOSFET
— Conventional MOSFET has already passed lower than 45nm transistor fabrication. As silicon is now hitting the atomic resolution and reaching its physical and electrical limitation, producing a proper working transistor tends to be more difficult and complicated. The major challenge is to fabricate a transistor with a nominal threshold voltage (V TH), lower gate leakage current (I OFF) and lower drain induced barrier lowering (DIBL). To overcome these problems, Silicon-on-insulator (SOI) MOSFET has been proposed, and it is believed to be capable of suppressing short channel effects (SCEs) by burying oxide layer in the silicon substrate. ATHENA and ATLAS module of SILVACO software were used in simulating the virtual fabrication and electrical performance of the transistors. An investigation on the characteristics and performance of the devices has been conducted in order to compare their electrical characteristics. The MOSFET structure was constructed by utilizing SILVACO Athena module, and the electrical characteristics were simulated using SILVACO Atlas module. The results of both the conventional bulk MOSFET and the SOI MOSFET were analyzed. It was observed that SOI MOSFET was superior compared to the conventional MOSFET in terms of their overall electrical characteristics.
Reducing short channel effects in dual gate SOI-MOSFETs with a drain dependent gate bias
2010 18th Iranian Conference on Electrical Engineering, 2010
In this paper we propose a new dual gate SOI-MOSFET in order to reduce short-channel effects (SCEs). In the proposed structure, the bias of the second gate which is near the drain is dependent on the drain voltage. To investigate transistor characteristics, a two-dimensional (2-D) analytical model for the surface potential variation along the channel is developed. A comparison between our structure and the single-gate (SG) SOI MOSFET demonstrates that short channel effects like, hot carriers effect and the drain induced barrier lowering (DIBL) are reduced considerably in the proposed structure.
Due to scaling of the channel length, SCEs and HCEs are becoming serious issues. To reduce these effects, electrically induced ultra-shallow source/drain junctions has been investigated using actual (Gaussian) source/drain doping profiles. In this paper the novel attributes of nano scale SOI MOSFETs with electrically induced source/drain junctions are presented with extensive simulation study. It has been found that the use of induced source/drain junctions is capable of controlling the short channel effects. Index Terms-Electrically induced source/drain junctions, hot electron effect, short channel effects, silicon-on-Insulator.
Reduction of the reverse short channel effect in thick SOI MOSFET's
IEEE Electron Device Letters, 2000
We show that the reverse short channel effect (RSCE) is reduced in NMOS devices made in thick silicon-oninsulator (SOI) material. The reduction of the RSCE depends on the thickness of the Si overlayer. It is found that the thinner the Si film, the less the threshold voltage roll-on. The experimental findings are explained by a decrease of the lateral distribution of silicon interstitials generated at the source and drain (S/D) region and are related with their high recombination velocity at the buried oxide. This method can be used to separately test the influence of S/D point defects on the RSCE from other different hypotheses reported in the literature. Coupled process-device simulation reveals that the method is very sensitive to fundamental point defect properties.
2003
A new two-dimensional analytical model for the potential distribution and drain-induced barrier lowering (DIBL) effect of fully depleted short-channel Silicon-on-insulator (SOI)-MESFET's has been presented in this paper. The two dimensional potential distribution functions in the active layer of the device is approximated as a simple parabolic function and the two-dimensional Poisson's equation has been solved with suitable boundary conditions to obtain the bottom potential at the Si/oxide layer interface. It is observed that for the SOI-MESFET's, as the gate-length is decreased below a certain limit, the bottom potential is increased and thus the channel barrier between the drain and source is reduced. The similar effect may also be observed by increasing the drain-source voltage if the device is operated in the near threshold or sub-threshold region. This is an electrostatic effect known as the drain-induced barrier lowering (DIBL) in the short-gate SOI-MESFET's. The model has been verified by comparing the results with that of the simulated one obtained by solving the 2-D Poisson's equation numerically by using the pde toolbox of the widely used software MATLAB.