Germanium p- & n-MOSFETs fabricated with novel surface passivation (plasma-PH3 and thin AlN) and TaN/HfO2 gate stack (original) (raw)
Related papers
HfO2 as gate dielectric on Ge: Interfaces and deposition techniques
Materials Science and Engineering: B, 2006
To fabricate MOS gate stacks on Ge, one can choose from a multitude of metal oxides as dielectric material which can be deposited by many chemical or physical vapor deposition techniques. As a few typical examples, we will discuss here the results from atomic layer deposition (ALD), metal organic CVD (MOCVD) and molecular beam deposition (MBD) using HfO 2 /Ge as materials model system. It appears that a completely interface layer free HfO 2 /Ge combination can be made in MBD, but this results in very bad capacitors. The same bad result we find if HfGe y (Hf germanides) are formed like in the case of MOCVD on HF-dipped Ge. A GeO x interfacial layer appears to be indispensable (if no other passivating materials are applied), but the composition of this interfacial layer (as determined by XPS, TOFSIMS and MEIS) is determining for the C/V quality. On the other hand, the presence of Ge in the HfO 2 layer is not the most important factor that can be responsible for poor C/V, although it can still induce bumps in C/V curves, especially in the form of germanates (Hf-O-Ge). We find that most of these interfacial GeO x layers are in fact sub-oxides, and that this could be (part of) the explanation for the high interfacial state densities. In conclusion, we find that the Ge surface preparation is determining for the gate stack quality, but it needs to be adapted to the specific deposition technique.
Interface-Engineered High-Mobility High- $k$ /Ge pMOSFETs With 1-nm Equivalent Oxide Thickness
IEEE Transactions on Electron Devices, 2009
High-k/germanium (Ge) interfaces are significantly improved through a new interface engineering scheme of using both effective pregate surface GeO 2 passivation and postgate dielectric (postgate) treatment incorporating fluorine (F) into a high-k/Ge gate stack. Capacitance-voltage (C-V) characteristics are significantly improved with minimum density of interface states (D it) of 2 × 10 11 cm −2 • eV −1 for Ge MOS capacitors. A hole mobility up to 396 cm 2 /V • s is achieved for Ge p-metaloxide-semiconductor field-effect transistors (pMOSFETs) with equivalent oxide thickness that is ∼10 Å and gate leakage current density that is less than 10 −3 A/cm 2 at V t ± 1 V. A high drain current of 37.8 μA/μm at V g − V t = V d = −1.2 V is presented for a channel length of 10 μm. The Ge MOSFET interface properties are further investigated using the variable-rise-and-fall-time charge-pumping method. Over three times D it reduction in both upper and lower halves of the Ge bandgap is observed with F incorporation, which is consistent with the observation that frequency-dependent flat voltage shift is much less for samples with F incorporation in the C-V characteristics of Ge MOS capacitors.
Surface Passivation of Germanium Using NH3 Ambient in RTP for High Mobility MOS Structure
2013
Ge CMOS is very striking for the post Si-CMOS technology. However, we have to attempt a number of challenges with regard to materials and their interface control. In this paper we have investigated the control of the interfacial properties of SiO2 / Ge gate stack structures by the thermal nitridation technique. Structural and electrical properties of SiO2 gate-dielectric metal-oxide-semiconductor (MOS) capacitors deposited by sputtering on germanium are studied. The structural characterization confirmed that the thin film was free of physical defects and smooth surface of the films after PDA at 500 °C in N2 ambient. The smooth surface SiO2 thin films were used for Pt / SiO2 / GeON / Ge MOS structures fabrication. The MOS structure yields a low leakage current density of 9.16 × 10 – 6A cm – 2 at 1 V.
Hf-based high-k dielectrics for p-Ge MOS gate stacks
Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, 2014
The physical and electrical properties of the gate stack high-k/Al 2 O 3 /GeO 2 /p-Ge were studied in detail, where the high-k is either HfO 2 or alloyed HfO 2 (HfZrO y , HfGdO x , or HfAlO x). Electrical measurements combined with x-ray photoelectron spectroscopy chemical bonding analysis and band alignment determination were conducted in order to assess the suitability of hafnium-based high-k for this kind of gate stacks, with emphasis on low density of interface states and border traps. HfAlO x was found to be the most promising high-k from those studied. The authors have also found that the current-voltage trends for the various systems studied can be explained by the band alignment of the samples obtained by our x-ray photoelectron spectroscopy analysis.
Applied Physics Letters, 2008
We demonstrate methodologies to improve the interface characteristics between a germanium ͑Ge͒ substrate and high-k gate dielectrics. GeON and SiO x were investigated as passivating layers on a Ge surface. Smaller hysteresis and interface state density ͑D it ͒ were obtained using SiO x interface layer and p-type metal oxide semiconductor field effect transistors ͑MOSFETs͒ fabricated with a gate stack of Ge/ SiO x / HfSiO/ WN showed about two times higher effective mobility compared to universal Si/ SiO 2 MOSFET. Because the formation of GeO x at the interface resulted in higher hysteresis and equivalent oxide thickness, the effective suppression of growth of unstable GeO x by SiO x interface layer contributed to the good device characteristics of the fabricated devices.
2008 IEEE International Electron Devices Meeting, 2008
High-k/Ge interfaces are significantly improved through a new interface engineering scheme of using both effective pre-gate surface GeO 2 passivation and post gate dielectric (post-gate) treatment incorporating fluorine (F) into high-k/Ge gate stack. Minimum density of interface states (D it) of 2 × 10 11 cm-2 eV-1 is obtained for Ge MOS capacitors. Hole mobility up to 396 cm 2 /Vs is achieved for Ge pMOSFETs with EOT ~10 Å and gate leakage current density less than 10-3 A/cm 2 at V t ± 1 V. Best drain current to date of 37.8 μA/μm at V g-V t = V d =-1.2V is presented for an L g of 10 µm. Variable rise and fall time charge pumping (CP) method is used to investigate Ge interface property and a significant D it reduction in both upper and lower half of bandgap is observed with F incorporation.
Study of CVD high- k gate oxides on high-mobility Ge and Ge/Si substrates
Thin Solid Films, 2006
Germanium is studied as a replacement candidate for silicon as channel material to enhance transistor performance. Interface states that cannot be passivated by standard forming gas anneals have been widely reported. In this work we demonstrate that thermal processing of a germanium/ HfO 2 stack leads to the formation of a hafnium germanate (HfGeO x ) that appears to be linked to these interface states. Our results suggest that interactions between HfO 2 and germanium can only be avoided by passivating the germanium with a capping layer. As an example, we discuss the use of a thin epitaxially grown Si layer that leads to greatly improved CV-characteristics. D
Microelectronic Engineering, 2013
Non-crystalline Hf Si oxynitrides Vacated O-site defects X-ray absorption spectroscopy (XAS) X-ray photoemission spectroscopy (XPS) C-V and J-V device measurements a b s t r a c t Three significant issues with respect to the ultimate scaling limitations of CMOS devices are (i) the channel or transport material, (ii) high-j compatible gate stacks: (a) the interface with the semiconductor substrate; (b) the high dielectrics, and (c) the gate metal, and (iii) the topological structure, planar, nano-tube, or in, etc. Two of these are high-lighted, focusing on (i) crystalline Ge, and transition metal dielectrics including specifically non-crystalline Hf Si oxynitrides, and nano-grain (a) ultra-thin 2 nm thick HfO 2 and TiO 2 . The research has demonstrated shallow trap interfacial slow trap densities of $5 Â 10 10 cm À2 , no detectable negative bulk fixed charges, and symmetric N-and P-MOCAPS in planar geometries. EOT values <0.5 nm were obtained for low-leakage current for N-MOSCAPS with ng-TiO 2 in contact with plasma processed c-Ge substrates.
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, 2009
Interfaces between crystalline-Si and high-K Hf-based oxide gate dielectrics have a lower-K interfacial transition region (ITR), generally 0.6–0.8nm SiON, which prevents reactions between Si and Hf precursors used in film deposition. These ITRs contribute ∼0.35nm to the equivalent oxide thickness limiting aggressive scaling. This article addresses Hf-based high-K gate dielectrics for devices on crystalline Ge substrates. The band gaps of GeO2 and Ge3N4 are reduced with respect to their Si counterparts, and as such may contribute to increased levels of interfacial defect states. A novel processing sequence is presented for (i) depositing HfO2 and Hf Si oxynitrides (HFSiON) onto N-passivated Ge(111) and Ge(100), and subsequently (ii) removing Ge–N interfacial bonding during 800°C thermal annealing in Ar. Near edge x-ray absorption spectroscopy and medium energy ion scattering measurements have confirmed that the interfacial nitrogen is indeed removed. However, there are reactions betw...