C4NP Cu-cored Pb-free flip chip interconnections (original) (raw)
Related papers
2007 Proceedings 57th Electronic Components and Technology Conference, 2007
Recently, the need of fine pitch flip chip interconnection has been continuously growing. In spite of this trend, solder flip chip interconnections have reached the limit in fine pitch applications of less than about 150µm pitch, because bump bridging between adjacent solder bumps occur. Therefore, the investigation on the fine pitch flip chip structure and its reliability are being needed. Metal column and solder double layered (=double bump) flip chip structure is one of the candidates for fine pitch applications. Double bump flip chip structure provides three advantages: 1) fine pitch flip chip interconnection less than 150µm due to straight shape of metal column bumps, 2) better thermo-mechanical reliability by changing the height of metal column bumps, and 3) high current-carrying capability due to excellent electrical conductivity of Cu as one of the column bump materials.
Investigation of flip chip under bump metallization systems of Cu pads
IEEE Transactions on Components and Packaging Technologies, 2002
In this study, UBM material systems for flip chip solder bumps on Cu pads were investigated using the electroless copper (E-Cu) and electroless nickel (E-Ni) plating methods; and the effects of the interfacial reaction between UBMs and Sn-36Pb-2Ag solders on the solder bump joint reliability were also investigated to optimize UBM materials for flip chip on Cu pads. For the E-Cu UBM, scallop-like Cu 6 Sn 5 intermetallic compound (IMC) forms at the solder/E-Cu interface, and bump fracture occurred along this interface under a relatively small load. In contrast, at the E-Ni/E-Cu UBM, E-Ni serves as a good diffusion-barrier layer. The E-Ni effectively limited the growth of the IMC at the interface, and the polygonal-shape Ni 3 Sn 4 IMC resulted in a relatively higher adhesion strength compared with the E-Cu UBM. As a result, electroless deposited UBM systems were successfully demonstrated as low cost UBM alternatives on Cu pads. It was found that the E-Ni/E-Cu UBM material system was a better choice for solder flip chip interconnection on Cu pads than the E-Cu UBM.
2009
In this paper we will present new cost-efficient solder bumping and adapted assembly technologies for the processing of flip-chips with a pitch of 100 µm or less and solder ball diameters of 60 µm or 50 µm, respectively. The wafer bumping has been realized using a highly efficient Wafer Level Solder Sphere Transfer (WLSST) process. This technology uses a patterned vacuum plate in order to simultaneously pick up all of the preformed solder spheres, optically inspect for yield, and then transfer them to the wafer at once. This paper will discuss this technology and the process parameters for producing fine pitch solder bumps. The flip-chips were assembled on special BT- and FR4-material using reflow soldering. Due to the large thermal expansion mismatch between substrate and chip, special epoxy based underfill has to be used in order to increase the long term reliability of the lead-free solder joints. The use of capillary flow as well as of no flow underfill and applicable design rul...
Design and Manufacturing of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications
Journal of Electronics Manufacturing, 2000
A novel and low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip is presented in this study. Emphasis is placed on the design, materials, process, manufacturing, and reliability of the micro VIP substrate of a chip scale package (CSP), and of the micro VIP CSP printed circuit board (PCB) assembly. Cross-sections of samples are examined for a better understanding of the solder bump, CSP redistribution, VIP, and solder joint. Non-linear finite element analyses are used to determine the stress and strain in the copper VIP and the solder joint. Time-dependent non-linear analysis is used to predict the thermal-fatigue life of the VIP solder joint.
C4NP - data for fine pitch to CSP flip chip solder bumping
2006 8th Electronics Packaging Technology Conference, 2006
To meet future requirements for cost, size, weight and electrical performance, microelectronic packaging is moving from wire bonds to solder bumps as the preferred method of interconnection from the device to the chip carrier or card. Flip chip in Package (FCiP) requires many small bumps on tight pitch whereas Wafer Level Chip Scale Packaging (WLCSP) typically requires much larger solder bumps on a greater pitch. Electroplating, solder paste printing and the direct attach of preformed solder spheres are technologies commonly used in volume production. Each of these techniques has limitations in scaling from fine pitch FCiP to WLCSP. Electroplating is better suited to fine pitch, whereas solder paste printing and solder sphere attachment work well for coarser pitches. C4NP (Controlled Collapse Chip Connection New Process) has proven to be suitable for this entire range of solder bump pitch. C4NP is a new solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into prefabricated and reusable glass templates (molds). The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. Filled mold and wafer are brought into close proximity/contact and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost, high yield and fast cycle time solution for both, fine-pitch FCiP as well as WLCSP bumping applications. This paper summarizes the latest manufacturing and reliability data for high-end logic device packaging using 300mm wafers bumped with C4NP. This includes reliability data for C4NP lead free solder bumped devices attached to organic chip carriers. Mold fill data for CSP type dimensions is included. Solder metrology data and yield information for fine pitch applications is summarized. Relevant process equipment technology and the unique requirements to run a high volume manufacturing C4NP process are reviewed. The paper also summarizes the C4NP manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques.
Flip chip assembly on PCB substrates with coined solder bumps
53rd Electronic Components and Technology Conference, 2003. Proceedings.
The objective of this work is to investigate the flip chip assembly on PCB substrates with coined eutectic solder bumps. In this study, stencil printed 37Pb/Sn solder flip chip bumping and subsequent coining processes were performed on both electroless Ni/Au and OSP (Organic Solderabilty Preservatives) finished PCBs, and then electroplated 97Pb/Sn flip chip bumped chips were successfully assembled. The structure, assembly processes, and reliability data of this package made of high melting temperature 97Pb/Sn flip chip bumps and etectic 37Pb/Sn PCB bumps interconnection were investigated. Reliability tests, using thermal cycling (-55 to 125 o C), PCT (Pressure Cooker Test), 85/85 (85 o C and 85 % humidity), and mechanical testing (die shear test) were performed. And daisy chain resistances were also measured to characterize the interconnections and to monitor degradation effects. Cross-section analysis was performed after reliablty tests to inspect flip chip solder joints with respect to phase transformation and growing of intermetallic compounds (IMCs) at the solder/PCB interfaces. From the experimental results, it was found that the combined bumps structure of 97Pb/Sn at chip and 37Pb/Sn at PCB was very reliable, and OSP finish was as good as Ni/Au finished PCB for these applicatons.
C4NP Technology for Lead Free Solder Bumping
2007 Proceedings 57th Electronic Components and Technology Conference, 2007
C4NP is a novel solder bumping technology developed by IBM that addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. It is a solder transfer technology where molten solder is injected into prefabricated and reusable glass molds. The glass mold contains etched cavities which mirror the bump pattern on the wafer. Filled mold and wafer are brought into close proximity/soft contact at reflow temperature and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. The simplicity of the process makes it a low cost, high yield and fast cycle time solution for bumping with a variety of high performance lead free alloys. The focus of this paper is on the mold fabrication, solder fill and inspection steps prior to solder transfer including high volume manufacturing tool designs. Yield improvements from the mold suppliers and mold specs are discussed. Finally, the results from a detailed cost model are reviewed. This cost model includes a comparison of C4NP versus alternative bumping techniques and includes capital, materials, and labor cost factors.