Dynamic Frequency Scaling Regarding Memory for Energy Efficiency of Embedded Systems (original) (raw)
Memory significantly affects the power consumption of embedded systems as well as performance. CPU frequency scaling for power management could fail in optimizing the energy efficiency without considering the memory access. In this paper, we analyze the power consumption and energy efficiency of an embedded system that supports dynamic scaling of frequency for both CPU and memory access. The power consumption of the CPU and the memory is modeled to show that the memory access rate affects the energy efficiency and the CPU frequency selection. Based on the power model, a method for frequency selection is presented to optimize the power efficiency which is measured using Energy-Delay Product (EDP). The proposed method is implemented and tested on a commercial smartphone to achieve about 3.3%-7.6% enhancement comparing with the power management policy provided by the manufacturer in terms of EDP. 1. INTRODUCTION Dynamic Voltage/Frequency Scaling (DVFS) has been used to reduce power consumption of computing systems. DVFS is a technique that increases or decreases the supply voltage by adjusting the operating frequency of CMOS circuits. CMOS circuits have static and dynamic power dissipation, and dynamic power dissipation is the dominant component in CMOS [1]. Most research on DVFS technique has focused on CPU DVFS [2], [3] because the CPU is the most power-consuming device when a computer system is actively running. Many contemporary OSs support DVFS of CPU. Linux's cpufreq [4] subsystem is an example. The frequency scaling technology is supported in hardware devices other than CPU such as the GPU or the memory bus, in such cases the operating frequency of the device can be managed by the user. For example, Linux system has a subsystem called devfreq to support frequency scaling of devices other than CPU [5]. Nexus 6 smartphone is a commercial mobile device supporting device frequency scaling, which allows us to adjust the clock speed of the memory bus that affects the memory bandwidth. Changing the frequency to access memory gives us another option to manage the power consumption of embedded systems. Attempts to manage the power consumption of memory access have been recently made. In [6], they proposed a DVFS method for DRAM based on memory bandwidth utilization. They devised a bandwidth-based frequency selection policy using their finding in experiments that memory latency is not significantly affected by the memory frequency at low bandwidth. But because memory hardware with DVFS support was not available, they emulated frequency scaling using timing delays. No DVFS is supported by DRAM so far because scaling of IO voltage on DRAM affects the stability and requires significant hardware change, but
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