Power analysis attack against encryption devices: a comprehensive analysis of AES, DES, and BC3 (original) (raw)

Power amount analysis: Another way to understand power traces in side channel attacks

2012 Second International Conference on Digital Information Processing and Communications (ICDIPC), 2012

Correlation power analysis, a method aiming to reveal the secrets of a cryptosystem, is based on one fixed time point of the captured power traces, which unveils the largest key dependent information leakage. In this paper, we propose a new power trace model based on communication theory to better understand and to efficiently exploit power traces in side channel attacks. Then, a new attack method denoted as Power Amount Analysis is proposed, which takes more time points into consideration compared to the correlation power analysis. Based on this trace model, we compare and discuss attack results produced by both methods at identical attack conditions. The superior efficiency of the Power Amount Analysis is demonstrated for an AES-128 encryption module. As an additional asset, this method features a high robustness in presence of randomly misaligned power traces.

Vulnerability modeling of cryptographic hardware to power analysis attacks

Integration, the VLSI Journal, 2009

Designers and manufacturers of cryptographic devices are always worried about the vulnerability of their implementations in the presence of power analysis attacks. This article can be categorized into two parts. In the first part, two parameters are proposed to improve the accuracy of the latest hypothetical power consumption model, so-called toggle-count model, which is used in power analysis attacks. Comparison between our proposed model and the toggle-count model demonstrates a great advance, i.e., 16%, in the similarity of hypothetical power values to the corresponding values obtained by an analog simulation. It is supposed that the attacker would be able to build such an accurate power model. Thus, in the second part of this article we aim at evaluating the vulnerability of implementations to power analysis attacks which make use of our proposed power model. Simple power analysis, various types of differential power analysis, and correlation power analysis are taken into account. Then, some techniques are proposed to examine the vulnerability of implementations to such kinds of power analysis attacks.

POWER AMOUNT ANALYSIS: AN EFFICIENT MEANS TO REVEAL THE SECRETS IN CRYPTOSYSTEMS

In this paper we propose a novel approach to reveal the information leakage of cryptosystems by means of a side-channel analysis of their power consumption. We therefore introduce first a novel power trace model based on communication theory to better understand and to efficiently exploit power traces in side-channel attacks. Then, we discuss a dedicated attack method denoted as Power Amount Analysis, which takes more time points into consideration compared to many other attack methods. We use the well-known Correlation Power Analysis method as the reference in order to demonstrate the figures of merit of the advocated analysis method. Then we perform a comparison of these analysis methods at identical attack conditions in terms of run time, traces usage, misalignment tolerance, and internal clock frequency effects. The resulting advantages of the novel analysis method are demonstrated by mounting both mentioned attack methods for an FPGA-based AES-128 encryption module.

Attacking AES-Masking Encryption Device with Correlation Power Analysis

International Journal of Communication Networks and Information Security (IJCNIS)

Modern communication system use cryptography algorithm to ensure data still confidentiality, integrity, and authentic. There is a new vulnerability in a cryptographic algorithm when implemented on a hardware device. This vulnerability is considered capable of uncovering a secret key used in a cryptographic algorithm. This technique is known as a power analysis attack. Previous and other research introduces countermeasure to countering this new vulnerability. Some researchers suggest using logic level with encoding the AES. The countermeasure using logic is meager cost and efficient. The contribution of this paper is to analyze CPA on encryption device that has been given logic level countermeasure. Our finding of this paper is the use of encoding with one-hot masking technique does not provide the maximum countermeasure effect against CPA-based attacks. In this research, CPA attack can be successfully revealing the AES secret-key

A Comparative Study of Power Consumption Models for CPA Attack

International Journal of Computer Network and Information Security, 2012

Power analysis attacks are types of side channel attacks that are based on analyzing the power consumption of the cryptographic devices. Correlation power analysis is a powerful and efficient cryptanalytic technique. It exploits the linear relation between the predicted power consumption and the real power consumption of cryptographic devices in order to recover the correct key. The predicted power consumption is determined by using the appropriate consumption model. Until now, only a few models have been proposed and used.

Anatomy of Differential Power Analysis for AES

2008

Abstract Side channel attacks are a significant threat to the deployment of secure embedded systems. Differential power analysis is one of the powerful power analysis attacks, which can be exploited in secure devices such as smart cards, PDAs and mobile phones. Several researchers in the past have presented experiments and countermeasures for differential power analysis in AES cryptography, though none of them have described the attack in a step by step manner, covering all the aspects of the attack.

Differential Power Analysis in AES: A Crypto Anatomy

International Journal of Engineering and Industries, 2011

Embedded systems are ubiquitous and are utilised for secure transactions. It is apparent that cashless wallets are the only future forward as handheld devices are already popular for payments. Side channel attacks are a significant threat to the deployment of secure embedded systems. Differential Power Analysis is one of the powerful power analysis attacks, which can be exploited in secure devices such as smart cards, PDAs and mobile phones. Several researchers in the past have presented experiments and countermeasures for Differential Power Analysis in AES cryptography, though none of them have described the attack in a step by step manner, covering all the aspects of the attack. Some of the important missing segments are the consideration of pipelines, analysis of the power profile to locate the points of attack, the correspondence of the source code, its assembly representation, and the point of attack. In this journal we describe in detail a step-wise explanation of the Differential Power Analysis of an AES implementation, with all of the aspects identified above.

Implementation of Power Analysis Attack using SASEBO-W Deevi

2014

Side Channel Attacks exploit information that leaks from a cryptographic device. Power Analysis is a kind of side channel attack which reveals the key of cryptographic device by analyzing its power consumption. Power analysis attack causes serious threat to the security of cryptographic devices. Differential Power Analysis Attack is most widely used against embedded devices but suffers from few defects. In this paper, SASEBO-W is used for implementing power analysis attack. The correlation power attack is used to recover secret key based on power consumption of the device. Keywords—Side Channel Attack, Power Analysis Attack, Differential Power Analysis, Correlation Power Analysis.

Power-Analysis Attack on an ASIC AES implementation

2004

. As a consequence, there is a growing interest in efficient implementations of the AES. For many applications, these implementations need to be resistant against side channel attacks, that is, it should not be too easy to extract secret information from physical measurements on the device. This article presents the first results on the feasibility of power analysis attack against an AES hardware implementation. Our attack is targeted against an ASIC implementation of the AES developed by the ETH Zurich. We show how to build a reliable measurement setup and how to improve the correlation coefficients, i.e., the signal to noise ratio for our measurements. Our approach is also the first step to link a behavior HDL simulator generated simulated power measurements to real power measurements.

Invariant of Enhanced AES Algorithm Implementations Against Power Analysis Attacks

Computers, Materials & Continua, 2022

The security of Internet of Things (IoT) is a challenging task for researchers due to plethora of IoT networks. Side Channel Attacks (SCA) are one of the major concerns. The prime objective of SCA is to acquire the information by observing the power consumption, electromagnetic (EM) field, timing analysis, and acoustics of the device. Later, the attackers perform statistical functions to recover the key. Advanced Encryption Standard (AES) algorithm has proved to be a good security solution for constrained IoT devices. This paper implements a simulation model which is used to modify the AES algorithm using logical masking properties. This invariant of the AES algorithm hides the array of bits during substitution byte transformation of AES. This model is used against SCA and particularly Power Analysis Attacks (PAAs). Simulation model is designed on MATLAB simulator. Results will give better solution by hiding power profiles of the IoT devices against PAAs. In future, the lightweight AES algorithm with false key mechanisms and power reduction techniques such as wave dynamic differential logic (WDDL) will be used to safeguard IoT devices against side channel attacks by using Arduino and field programmable gate array (FPGA).