Temperature-aware microarchitecture (original) (raw)
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Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization, 2004
With cooling costs rising exponentially, designing cooling solutions for worst-case power dissipation is prohibitively expensive. Chips that can autonomously modify their execution and powerdissipation characteristics permit the use of lower-cost cooling solutions while still guaranteeing safe temperature regulation. Evaluating techniques for this dynamic thermal management (DTM), however, requires a thermal model that is practical for architectural studies.
Temperature-Aware Microarchitecture: Extended Discussion and Results
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processor-level techniques that can regulate operating temperature when the package's capacity is exceeded. Evaluating such techniques, however, requires a thermal model that is practical for architectural studies.
Temperature-aware microarchitecture : extended results and discussion
2003
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processor-level techniques that can regulate operating temperature when the package's capacity is exceeded. Evaluating such techniques, however, requires a thermal model that is practical for architectural studies.
Granularity of microprocessor thermal management: a technical report
Process technology scaling, poor supply voltage scaling and the resultant exponential increase in power density have made temperature a first-class design constraint in today's microprocessors. An interesting question in the context of thermal management and multi-core architectures is about the correct size granularity of thermal management. It is known that the silicon substrate acts as a spatial low-pass filter for temperature. This means that if blocks with very high power density are small enough (for e.g., if they are below a "cut-off " size), they do not cause hot spots. This paper investigates this phenomenon analytically and presents a discussion through three microarchitectural examples. First is a thermal study of a many-core architecture which illustrates the thermal benefit of many small cores as opposed to a few large cores. This study also explores the effect of local vs. global thermal management. Second is an investigation of whether high aspect ratio sub-blocks such as cache lines can become hot spots due to pathological code behaviour. Third is an exploration of thermal sensor accuracy as a function of the number of sensors and a characterization of two sensor interpolation schemes as a means to reduce sensor errors.
Sustainable Computing: Informatics and Systems, 2011
Temperature-aware techniques have established themselves as crucial steps during the design and operation of new complex ICs (e.g. dual-core microprocessors) in order to protect the ICs against high temperatures that may drastically reduce their lifetime or even render them inoperable. These techniques have been developed after it became clear that power-aware techniques and low-power design are insufficient since they still allowed hotspots to develop in the chip with temperatures considerably higher than the average temperature. The goal of this paper is to provide an overview of the state-of-the-art of temperature-aware computing. After a brief introduction, we present the current approaches to measuring the temperature of a circuit during its operation and to estimating, during the design phase, the maximum temperature that the circuit will experience. We then survey the known techniques for designing a chip with lower maximum temperature. This is followed by reviewing the currently employed run-time temperature management techniques. This paper presents a thorough review of the research done in the past decade or so in the field of thermal-aware computing and lists most of the relevant journal and conference papers on this topic.
Temperature-aware computing - University of
2010
Temperature-aware techniques have established themselves as crucial steps during the design and operation of new complex ICs (e.g. dual-core microprocessors) in order to protect the ICs against high temperatures that may drastically reduce their lifetime or even render them inoperable. These techniques have been developed after it became clear that power-aware techniques and low-power design are insufficient since they still allowed hotspots to develop in the chip with temperatures considerably higher than the average temperature. The goal of this paper is to provide an overview of the state-of-the-art of temperature-aware computing. After a brief introduction, we present the current approaches to measuring the temperature of a circuit during its operation and to estimating, during the design phase, the maximum temperature that the circuit will experience. We then survey the known techniques for designing a chip with lower maximum temperature. This is followed by reviewing the currently employed run-time temperature management techniques. This paper presents a thorough review of the research done in the past decade or so in the field of thermal-aware computing and lists most of the relevant journal and conference papers on this topic.
HotSpot: Techniques for Modeling Thermal Effects at the Processor-Architecture Level
This paper describes a thermal-modeling approach that is easy to use and computationally efficient for modeling thermal effects and thermal-management techniques at the processor architecture level. Our approach models thermal behavior of the die and its package as a circuit of thermal resistances and capacitances that correspond to functional blocks at the architecture level. This yields a simple model that still accounts for heating in individual architecture-level blocks, while also capturing heat flow among blocks and through the package. A model like this that can be integrated with cyclelevel microarchitecture simulators is needed, because the architecture community has demonstrated growing interest in thermal management, but currently lacks any way to model on-chip temperatures in a tractable way.
HotSpot: a dynamic compact thermal model at the processor-architecture level
Microelectronics Journal, 2003
This paper describes a thermal-modeling approach that is easy to use and computationally efficient for modeling thermal effects and thermal-management techniques at the processor architecture level. Our approach is based on modeling thermal behavior of the microprocessor die and its package as a circuit of thermal resistances and capacitances that correspond to functional blocks at the architecture level. This yields a simple compact model, yet heat dissipation within all major functional blocks and the heat flow among blocks and through the package are accounted for. The model is parameterized, boundary-and initial-conditions independent, and is derived by a structure assembly approach. The architecture community has demonstrated growing interest in thermal management, but currently lacks a way to model on-chip temperatures in a tractable way. Our model can be used for initial exploration of the design space at the architecture level. The model can easily be integrated into popular power/performance simulators, can be used to determine how thermal stress is correlated to the architecture, and how architecture-level design decisions influence thermal behavior and related effects. q
Enhanced thermal management for future processors
2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408), 2003
An enhanced thermal management mechanism that reduces power by scaling frequency and voltage in response to excessive temperatures is presented. The voltage transition process is done transparently to the execution of applications.