The third lecture / electronic circuit design course (original) (raw)
Related papers
Performance characterization of MOS turn off thyristors
Scripta Materialia, 2000
Recently, power semiconductor devices that combine the technology of MOS turn-o[f and bipolar conduction have been introduced for operation at high voltage and hi h current levels. The MOS Turn Off thyristor (MTO ) is a switching device based on the Gate Turn Off Thyristor. This paper is devoted to presenting the results from a study performed to examine the operating characteristics of the MTOTM. The study included experimental measurements of on-state properties and switching characteristics under snubberless hard switching. Turn off loss; device switching delay time, storage time, transition time and on-state losses are characterized. In addition to the experimental results, the paper also presents a brief review of operation of the device and the experimental procedure used in the study. Ti5
MOS-thyristor devices with high voltage and current capabilities may replace conventional thyristors and IGBTs in high power applications. However, the maximum controllable current density (J mcc ), the current saturation capability and the total transient losses have to be improved. This article is addressed to the comparison of the electrical charateristics of MOS-thyristor structures including a Floating Ohmic Contact to provide high packing density and current saturation capability. The operation mode of both structures is analyzed with the aid of numerical simulations and experimental results, obtained from 1200 V devices, are provided to compare their electrical characteristics. ᭧ 1999 Elsevier Science Ltd. All rights reserved.
Solid-State Electronics, 1992
The failure mechanisms of Gate-Turn-Off (GTO) thyristors are investigated. Measurements based on a time-resolved free-carrier absorption (FCA) technique are used to support the presented models. The measurements serve to map the local carrier densities two-dimensionally, at any time of the switching cycle. Inductively loaded GTOs under snubberless operation are studied close to the safeoperating area (SOA) limit. Several important features of the destructive process are established. First, the existence of a quasi space-charge region, QSC, in the n base and charge focusing at the anode side of the device is noticed during the fall-time period. Secondly, a piling up of holes in the p base is followed by current filamentation during the tail period. The sequential behaviour of different phenomena and their possible causal explanations are also established. The expansion of the QSC towards the anode emitter causes the enhancement and focusing of the charge distribution in the vicinity of this junction. Two possible failure mechanisms, viz. local dynamic punch-through in the n base and local dynamic avalanche injection in the blocking junction are discussed in the light of the experimental results. It is also suggested that both the above mentioned failure mechanisms can be part of the chain of events leading to device failure. Regardless of which mechanism dominates, a high peak of excess holes appears in the p base in the beginning of the tail period. This charge debiases the cathode junction locally, i.e. compensates the negative bias of the cathode junction, and current filaments connecting the cathode and anode sides of the device are formed. The excessive power dissipation in the dominant filament causes failure and permanent damage.
Physical Features of the Barrier-Controlled Blocking Function of the Static Induction Thyristor
IEEE Transactions on Electron Devices, 2011
The physical features of the barrier-controlled blocking function of static induction thyristors (SITHs) are elaborated in detail from a new point of view. The correlative subjects are experimentally studied. The geometrical structure, the fabrication technology, the biasing conditions, the I-V characteristic, the conception, and the definition of the channel pinchoff of the SITH are discussed. Emphases are on the new ideas of the channel-barrier formation, the features of the channel barrier, the relationship between the barrier and the geometrical structure, and the biasing conditions. The physical mechanisms of the capability of blocking the current and bearing a high voltage are analyzed in depth.
Accurate calculations of the forward drop and power dissipation in thyristors
IEEE Transactions on Electron Devices, 1978
Four-layer power thyristors are analyzed using exact numerical solutions of the full set of semiconductor device equations together with the heat-flow equation. Included in the analysis are the physical mechanisms of carrier-carrier scattering, Auger and SRH recombination, and band-gap narrowing. The experimental current-voltage curves for three-thyristor structures are compared with the theoretical predictions and are shown to be in good agreement. The limiting effects on device behavior of the physical mechanisms noted above, including heat-sink thermal impedance, are investigated over the range of device operating conditions. The distribution of power dissipation throughout the device is shown and compared with the distribution of recombination in the device. The theory of calculating power dissipation in a semiconductor is also discussed.
Three-dimensional model of gate current flow in thyristor. I. Description
IEEE Transactions on Electron Devices, 1990
The digital gate concept is one of the fundamental ways leading to improvement of the dynamic rates of a thyristor. The distribution of the current density of the gate-cathode junction along the edge of the gate contact must, however, be as uniform as possible. A numerical model which permits determination of this distribution, the initial turn-on area, and their dependence
Thyristor and their applications
International journal of applied research, 2017
This chapter is basically depend on basic information about SCR (Silicon Controlled Rectifier) it’s characteristics. How SCR is different from diode and methods of turn on of scr. Its application in converter, inverter and chopper circuit.