Review Paper on Placement Algorithms (original) (raw)

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A Sea-of-Gates Style FPGA Placement Algorithm

VLSI Design, 1996

Field Programmable Gate Arrays (FPGAs) have a pre-defined chip boundary with fixed cell locations and routing resources. Placement objectives for flexible architectures (e.g., the standard cell design style) such as minimization of chip area do not reflect the primary placement goals for FPGAs. For FPGAs, the layout tools must seek 100% routability within the architectural constraints. Routability and congestion estimates must be made directly based on the demand and availability of routing resources for detailed routing of the particular FPGA. We. present a hierarchical placement approach consisting of two phases: a global placement phase followed by a detailed placement phase. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routability of the FPGA by considering factors which cause congestion at the detailed routing level and to precisely satisfy all ...

FPGA Placement using Space Filling Curves: Theory Meets Practice 1

Research in VLSI placement, an NP-hard problem, has branched in two different directions. The first one employs iterative heuristics with many tunable parameters to produce near-optimal so- lution but without theoretical guarantee on its quality. The other one considers placement as graph embedding and designs approximation algorithms with provable bounds on the quality of the solution. In this paper, we aim at unifying the above two directions. First, we extend the existing approximation algorithms for graph embedding in 1D and 2D mesh to those for hyper- graphs, which typically model circuits to be placed on a FPGA. We prove an O(d p log nlog log n) approximation bound for 1D and O(dlog nlog log n) approximation bound for the 2D mesh, where d is the maximum degree of hyperedges and n the number of vertices in the hypergraph. Next, we propose an efficient method based on linear arrangement of the CLBs, and the notion of space filling curves, for placing the configurable logic block...

A New Paradigm for FPGA Placement Without Explicit Packing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019

Placement and packing are two important but separated optimization steps in a conventional FPGA implementation flow. A packing engine clusters logic elements, like lookup tables (LUTs) and flip-flops (FFs), into configurable logic blocks (CLBs), while a placement engine determines their physical locations in FPGA layouts. This paper presents a new paradigm for FPGA placement without an explicit packing stage. In the proposed framework, the solution spaces of placement and packing are simultaneously explored in a smooth and elegant way. Our experiments on ISPD 2016 and 2017 benchmark suites demonstrate the effectiveness of the proposed framework.

Hierarchical FPGA placement Positionnement hí erarchique sur FPGA

Field-programmable gate arrays (FPGAs) are semiconductor chips that can realize most digital circuits on site by specifying programmable logic and their interconnections. The use of FPGAs has grown almost exponentially because they dramatically reduce design turnaround time and startup cost for electronic products compared with traditional application-specific integrated circuits (ASICs). Efficient computer-aided-design tools are required to compile hardware descriptions into bitstream files that are used to configure the target FPGA to implement the desired circuits. Currently, the compile time, which is dominated by placement and routing time, can easily be hours or even days for large (8-million-gate) FPGAs. With 40-million-gate FPGAs on the horizon, these prohibitively long compile times may nullify the time-to-market advantage of FPGAs. This paper presents two novel placement heuristics that significantly reduce the computation time required to achieve high-quality placements, compared with the versatile place and route (VPR) tool. The first algorithm is an enhancement of simulated annealing (SA) that attempts to solve the placement problem top-down by considering all modules at the flat level. The second algorithm involves a hierarchical approach based on a two-step procedure that first proceeds bottom-up (grouping highly connected modules together) and then top-down (declustering). The overall effect is to reduce the number of entities needing to be considered at each level, such that time-consuming methods like SA become feasible for very large problems. Experimental results show a 70–80% reduction in runtime, coupled with very high-quality placements. Les réseaux logiques programmables (FPGA) sont des circuits pouvant réaliser la majorité des tâches de circuits numériques en programmant les portes logiques et leurs interconnections. L'utilisation de FPGA s'est développée presque exponentiellement parce que ces circuits réduisent nettement les délais de conception ainsi que les coûts de production comparativementà des circuits intégréesà applications spécifiques (ASIC). Des outils d'aidè a la conception par ordinateur efficaces sont requis pour la compilation de la description matérielle dans le fichier de configuration du FPGA afin d'implémenter les circuits désirés. Actuellement le temps de compilation pour des applications FPGA d'envergure (8 millions de portes logiques) est majoritairement composé du temps de positionnement et du choix des parcours des signaux. Ce temps peut aisément prendre des heures et même des jours. Avec la disponibilité prochaine de circuits FPGA de 40 millions de portes logiques en vue, ces temps de compilation prohibitifs peuvent annuler l'avantage des FPGA sur les ASIC en termes de temps de mise en marché. Cet article présente deux nouvelles méthodes de positionnement heuristique qui réduisent significativement le temps de calculs requis pour atteindre des positionnements de haute qualité, par rapportà l'outil habituel de placement et de routage (VPR). Le premier algorithme est une amélioration du recuit simulé (SA) qui tente de résoudre leprobì eme de positionnement du haut vers le bas en considérant tous les modulesà un niveau uniforme. Le second algorithme est une approche hiérarchique basée sur une procédure en deuxétapes qui débute du bas vers le haut (regroupant des modules hautement connectés ensemble) et ensuite du haut vers le bas (distribution). L'effet global est de réduire le nombre d'entités requisesà chaque niveau, de tellemanì ere que des méthodes longues comme le SA deviennent réalisables pour desprobì emes d'envergure. Les résultats expérimentaux montrent une réduction du temps d'exécution de l'ordre de 70–80 %, tout en ayant des positionnements de grande qualité.

FPGA placement using space-filling curves: Theory meets practice

ACM Transactions on …, 2009

Research in VLSI placement, an NP-hard problem, has branched in two different directions. The first one employs iterative heuristics with many tunable parameters to produce a near-optimal solution but without theoretical guarantee on its quality. The other one considers ...

FPGA placement using space-filling curves

ACM Transactions on Embedded Computing Systems, 2009

Research in VLSI placement, an NP-hard problem, has branched in two different directions. The first one employs iterative heuristics with many tunable parameters to produce near-optimal solution but without theoretical guarantee on its quality. The other one considers placement as graph embedding and designs approximation algorithms with provable bounds on the quality of the solution. In this paper, we aim at unifying the above two directions. First, we extend the existing approximation algorithms for graph embedding in 1D and 2D mesh to those for hypergraphs, which typically model circuits to be placed on a FPGA. We prove an O(d √ log n log log n) approximation bound for 1D and O(d log n log log n) approximation bound for the 2D mesh, where d is the maximum degree of hyperedges and n the number of vertices in the hypergraph. Next, we propose an efficient method based on linear arrangement of the CLBs, and the notion of space filling curves, for placing the configurable logic blocks (CLBs) of a netlist on island-style FPGAs with an approximation guarantee of O(d 4 √ log n √ k log log n). For the set of FPGA placement benchmarks, the running time is near-linear in the number of CLBs, thus allowing for scalability towards large circuits. We obtained on an average a 33× speedup with only 1.31× degradation in the quality of solution with respect to that produced by the popular FPGA tool VPR, thereby demonstrating the suitability of this very fast method for FPGA placement, with a provable performance guarantee.

Fast FPGA Placement using Space-filling Curve

2005

In this paper, we propose a placement method for islandstyle FPGAs, based on recursive bi-partitioning followed by application of space-filling curves. Experimental results of our method show 55% improvement in cost, when compared to random initial placement of the popular tool VPR. The solutions thus obtained require 44.5% fewer moves during final iterative refinement by ultra-low temperature simulated annealing, whereas the quality of solution is on the average 0.1% better. This establishes the utility of the method for fast reconfiguration of FPGA based co-processors.

Placement and Routing for Performance-Oriented FPGA Layout

VLSI Design, 1998

This paper presents a performance-oriented placement and routing tool for fieldprogrammable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wirelength. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route several benchmarks.

VPR: A new packing, placement and routing tool for FPGA research

Field-Programmable Logic and Applications, 1997

We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which we can compare. Although the algorithms used are based on previously known approaches, we present several enhancements that improve run-time and quality. We present placement and routing results on a new set of large circuits to allow future benchmark comparisons of FPGA place and route tools on circuit sizes more typical of today's industrial designs.

An Algorithm for Dynamically Reconfigurable FPGA Placement

International Conference on Computer Design, 2001

In this paper, we introduce a new placement problem motivated by the Dynamically Reconfigurable FPGA (DRFPGA) architectures. Unlike traditional placement, the problem for DRFPGAs must consider the precedence constraints among logic components. For the placement, we develop an effective metric that can consider wirelength, register requirement, and power consumption simultaneously. With the considerations of the new metric and the precedence constraints, we then present a three-stage scheme of partitioning, initial placement generation, and placement refinement to solve the new placement problem. Experimental results show that our placement scheme with the new metric achieves respective improvements of 17.2%, 27.0%, and 35.9% in wirelength, the number of registers, and power consumption requirements, compared with the list scheduling method