InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers (original) (raw)
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IEEE Electron Device Letters, 2000
The selectively implanted buried subcollector (SIBS) is a method to decouple the intrinsic and extrinsic BC of InPbased double-heterojunction bipolar transistors (DHBTs). Similar to the selectively implanted collector (SIC) used in Si-based bipolar junction transistors (BJTs) and HBTs, ion implantation is used to create a N+ region in the collector directly under the emitter. By moving the subcollector boundary closer to the BC junction, SIBS allows the intrinsic collector to be thin, reducing , while simultaneously allowing the extrinsic collector to be thick, reducing BC . For a 0.35 6 m 2 emitter InP-based DHBT with a SIBS, 6 fF total BC and 6 V BV CBO were obtained with a 110-nm intrinsic collector thickness. A maximum of 252 GHz and MAX of 283 GHz were obtained at a CE of 1.6 V and of 7.52 mA. Despite ion implantation and materials regrowth during device fabrication, a base and collector current ideality factor of 2 0 and 1 4, respectively, at an of 100 A, and a peak dc of 36 were measured. Index Terms-Heterojunction bipolar transistors (HBTs), ion implant, InP, molecular-beam epitaxy (MBE).
Solid-State Electronics, 2005
We have demonstrated InP/InGaAs/InP MBE-grown DHBTs fabricated with patterned sub-collector by elevated temperature 200°C N+ implant and subsequent device material over growth. F t /F max > 250 GHz/300 GHz were obtained on DHBTs with 0.35 lm · 6 lm emitters from this process. Ring oscillators fabricated with this process showed good uniformity with 82% of yield on wafers and an average gate delay of 8 ps. Difference of surface morphology on re-grown DHBT layers over elevated temperature implanted and room temperature 22°C implanted sub-collector was observed.
Selectively Implanted Subcollector DHBTs
2006 International Conference on Indium Phosphide and Related Materials Conference Proceedings, 2006
In 0.53 Ga 0.47 As/InP double heterojunction bipolar transistors with implanted subcollectors have been designed and fabricated to eliminate the base access pad capacitance. A blanket Fe implant eliminates the interface charge and a patterned Si implant creates an isolated
InP DHBT IC Technology with Implanted Collector Pedestal and Electroplated Device Contacts
2006 IEEE Compound Semiconductor Integrated Circuit Symposium, 2006
We report the development of a wide bandwidth InP double heterojunction bipolar transistor technology that incorporates an ion implanted N + collector-pedestal for reduction of extrinsic collector-base capacitance C cb . The technology also utilizes novel electroplating processes and dielectric sidewall spacers to eliminate traditional liftoff processes from the formation of a self-aligned base-emitter junction. Devices with 0.4 µm emitter junction widths demonstrate peak f τ and f max values of over 370 GHz. Importantly, the devices also demonstrate a significant reduction (~35%) in C cb versus HBTs with the same device footprint fabricated without a collector pedestal. Static frequency-divider circuits have been realized in the technology. A CML divide-by-two circuit demonstrated a maximum operating frequency of 128 GHz. This result demonstrated a ~20% improvement in operating frequency versus the same design realized in a non-collector-pedestal process.
Submicron InP-based HBTs for Ultra-high Frequency Amplifiers
International Journal of High Speed Electronics and Systems, 2003
Transistor bandwidths are approaching terahertz frequencies. Paramount to high speed transistor operation is submicron device scaling. High bandwidths are obtained with heterojunction bipolar transistors by thinning the base and collector layers, increasing emitter current density, decreasing emitter contact resistivity, and reducing the emitter and collector junction widths. In mesa HBTs, minimum dimensions required for the base contact impose a minimum width for the collector junction, frustrating device scaling. We have fabricated HBTs with narrow collector junctions using a substrate transfer process. HBTs with submicron collector junctions exhibit extremely high fmaxand high gains in mm-wave ICs. Transferred-substrate HBTs have obtained record 21 dB unilateral power gain at 100 GHz. Recently-fabricated devices have shown unbounded unilateral power gain from 40-110 GHz, and fmaxcannot be extrapolated from measuremente. However, these devices exhibited high power gains at 220 GHz...
InP HBTs for THz frequency integrated circuits
2011
A 0.25μm InP DHBT process has been developed for THz frequency integrated circuits. A 0.25×4μm2 HBT exhibits an extrapolated ft/fmax of 430GHz/1.03THz at IC=11mA, VCE=1.8V. The transistors achieve this performance while maintaining a common-emitter breakdown voltage (BVCEO)>;4V. Thin-film interconnects and backside wafer processes have been developed to support selected IC demonstrations. The technology has been used to build fundamental oscillators, amplifiers and dynamic frequency dividers all operating at >;300GHz. Additionally, increasingly complex circuits such as a full PLL have been demonstrated.
InP HBT Technologies for THz Integrated Circuits
Proceedings of the IEEE, 2017
A 0.25m InP DHBT process has been developed for THz frequency integrated circuits. A 0.25x4m 2 HBT exhibits an extrapolated f t /f max of 430GHz/1.03THz at I C =11mA, V CE = 1.8V. The transistors achieve this performance while maintaining a common-emitter breakdown voltage (BV CEO) >4V. Thin-film interconnects and backside wafer processes have been developed to support selected IC demonstrations. The technology has been used to build fundamental oscillators, amplifiers and dynamic frequency dividers all operating at >300GHz. Additionally, increasingly complex circuits such as a full PLL have been demonstrated.
InP HBT IC Technology for Terahertz Frequencies: Fundamental Oscillators Up to 0.57 THz
IEEE Journal of Solid-State Circuits, 2000
We report on the development of a 0.25-m InP HBT IC technology for lower end of the THz frequency band (0.3-3 THz). Transistors demonstrate an extrapolated of 800 GHz while maintaining a common-emitter breakdown voltage (BVCEO) 4 V. The transistors have been integrated in a full IC process that includes three-levels of interconnects, and backside processing. The technology has been utilized for key circuit building blocks (amplifiers, oscillators, frequency dividers, PLL, etc), all operating at 300 GHz.
IEEE Transactions on Electron Devices, 2000
Recent attempts to achieve 400 GHz or higher f T and f M AX with InP heterojunction bipolar transistors (HBTs) have resulted in aggressive scaling into the deep submicrometer regime. In order to alleviate some of the traditional mesa scaling rules, several groups have explored selectively implanted buried subcollectors (SIBS) as a means to decouple the intrinsic and extrinsic collector design. This allows τ C to be minimized without incurring a large total C BC increase, and hence, a net improvement in f T and f M AX is achieved. This paper represents the first investigation into the series resistance and capacitance characteristics of submicrometer-width SIBS regions (as narrow as 350 nm) for InP double HBTs. Although the SIBS resistance is higher than that of epitaxially grown layers, the SIBS concept is able to provide good dopant activation and a significant decrease in C BC . S-parameter measurements are presented to clarify the impact of SIBS geometry variations, caused by both intentional device design and process variations, on f T and f M AX . Parasitic resistances and high background doping limit the f T improvement, but the C BC reduction is sufficient to demonstrate a 30% increase in f M AX . Results indicate that further improvements in f T and f M AX using the SIBS concept will be possible.
Collector-pedestal InGaAs/InP DHBTs fabricated in a single-growth, triple-implant process
IEEE Electron Device Letters, 2000
This letter reports InP/In 0.53 Ga 0.47 As/InP double heterojunction bipolar transistors (DHBTs) employing an N + subcollector and N + collector pedestal-formed by blanket Fe and patterned Si ion implants, intended to reduce the extrinsic collector-base capacitance C cb associated with the device footprint. The Fe implant is used to compensate Si within the upper 130 nm of the N + subcollector that lies underneath the base ohmic contact, as well as compensate the ∼ 1 − 7 × 10 −7 C/cm 2 surface charge at the interface between the indium phosphide (InP) substrate and the N − collector drift layer. By implanting the subcollector, C cb associated with the base interconnect pad is eliminated, and when combined with the Fe implant and selective Si pedestal implant, further reduces C cb by creating a thick extrinsic collector region underneath the base contact. Unlike previous InP heterojunction bipolar transistor collector pedestal processes, multiple epitaxial growths are not required. The InP DHBTs here have simultaneous 352-GHz f τ and 403-GHz f max . The dc current gain β ≈ 38, BV ceo = 6.0 V, BV cbo = 5.4 V, and I cbo < 50 pA at V cb = 0.3 V. Index Terms-Collector pedestal, heterojunction bipolar transistor (HBT), indium phosphide (InP), ion implantation.