Architecture of a low-complexity non-binary LDPC decoder (original) (raw)

2008 Second International Conference on Electrical Engineering, 2008

Abstract

In this paper, we propose a hardware implementation of the EMS decoding algorithm for non-binary LDPC (NB- LDPC) codes, presented in [4]. To the knowledge of the authors this is the first implementation of an GF(q) LDPC decoder for high order fields (q ges 64). The originality of the proposed architecture is that it takes into account the memory problem

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