Fault Diagnosis in Integrated Circuits with BIST (original) (raw)

Scan-based BIST fault diagnosis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999

Existing built-in self-test (BIST) diagnostic techniques assume the existence of a few bit errors in a test response sequence. This assumption is unrealistic since in a BIST environment a single defect can usually cause hundreds or thousands of errors in a test response sequence. Without making the above assumption, this paper presents a novel BIST fault diagnostic technique for scan-based

An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits

Asia and South Pacific Design Automation Conference, 1999

Design of an adaptive built-in-self-test (BIST) scheme for detecting multiple stuck-open faults in a CMOS complex cell is proposed. The test pattern generator (TPG) adaptively generates a subset of single- input-change (SIC) test pairs based on the past responses of the circuit under test (CUT). The design is universal, i.e., independent of the structure and functionality of the CUT. The

1An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits

2014

Abstract: Design of an adaptive built-in-self-test (BIST) scheme for detecting multiple stuck-open faults in a CMOS complex cell is proposed. The test pattern generator (TPG) adaptively generates a subset of single-input-change (SIC) test pairs based on the past responses of the circuit under test (CUT). The design is universal, i.e., independent of the structure and functionality of the CUT. The average length of the test sequence (TS) in an n-input CUT is (n+1).2n [(n+1).2n-1] in a fault-free [faulty] condition. The response analyzer (RA) is also simple to design. All robustly testable multiple stuck-open faults (occurring simultaneously both in n- and p-parts) can be detected using the proposed BIST scheme. I.

IJERT-A BIST CIRCUIT FOR FAULT DETECTION USING PSEUDO EXHAUSTIVE TWO PATTERN GENERATOR

International Journal of Engineering Research and Technology (IJERT), 2012

https://www.ijert.org/a-bist-circuit-for-fault-detection-using-pseudo-exhaustive-two-pattern-generator https://www.ijert.org/research/a-bist-circuit-for-fault-detection-using-pseudo-exhaustive-two-pattern-generator-IJERTV1IS5228.pdf Built-in self test (BIST) has been accepted as an efficient alternative to external testing, since it provides for both test generation and response verification operations, on chip. Pseudo-exhaustive BIST generators provide 100% fault coverage for detectable combinational faults with much fewer test vectors than exhaustive testing. An (n, k) adjacent bit pseudo-exhaustive test set (PETS) is a set of n-bit vectors in which all 2k binary combinations appear to all adjacent k-bit groups of inputs. Pseudoexhaustive testing evolves applying all possible input test patterns to the each output cones to test the functionality of a combinational circuit. It provides high fault coverage of detectable combinational faults with minimum number of test patterns than the conventional exhaustive test pattern generation. In (n,k)-adjacent bit pseudo-exhaustive test sets, all 2k binary combinations appear to all adjacent k-bit of input groups. With recursive pseudoexhaustive generation, all (n,k) adjacent bit pseudoexhaustive test patterns are generated for k ≤ n and more than one modules can be tested in parallel. The two pattern test is used to detect sequential faults such as stuck-open faults in CMOS circuits. Delay testing is also used to assure correct circuit operation at regular clock speeds requires two pattern testing. Here pseudoexhaustive two pattern generator is presented and all (n,k) adjacent bit pseudoexhaustive tests are generated for k ≤ n recursively.