Diagnostic Modelling of Digital Systems with Multilevel Decision Diagrams (original) (raw)

Diagnostic modeling of microprocessors with high-level decision diagrams

2008 11th International Biennial Baltic Electronics Conference, 2008

Automated test generation for digital systems encompasses three activities: selecting a description method, developing a fault model and generating tests to detect the faults covered by the fault model. The efficiency of test generation (quality, speed) is highly depending on the description method and fault models. As the complexity of digital systems continues to increase, the gate level test generation methods have become obsolete. Promising approaches are high-level methods. In this paper, a method for describing microprocessors as a special case of digital systems is explained and modeling faults with High-Level Decision Diagrams (HLDD) is presented. HLDDs serve as a basis for a general theory of test generation for mixed-level representations of systems, similarly as we have Boolean algebra for logic-level. HLDDs can be used for representing systems uniformly either at logic-level, highlevel or simultaneously at both levels. The fault model on HLDDs represents a generalization of the classical gatelevel stuck-at fault model to higher levels-the latter was defined for Boolean expressions whereas the former is defined for nodes in HLDDs having more general interpretation.

Modeling microprocessor faults on high-level decision diagrams

2008

Automated test generation for digital systems encompasses three activities: selecting a description method, developing a fault model and generating tests to detect the faults covered by the fault model. The efficiency of test generation (quality, speed) is highly depending on the description method and fault models. As the complexity of digital systems continues to increase, the gate level test generation methods have become obsolete. Promising approaches are high-level methods. In this paper, a method for describing microprocessors as a special case of digital systems is explained and modeling faults with High-Level Decision Diagrams (HLDD) is presented. HLDDs serve as a basis for a general theory of test generation for mixed-level representations of systems, similarly as we have Boolean algebra for logic-level. HLDDs can be used for representing systems uniformly either at logic-level, highlevel or simultaneously at both levels. The fault model on HLDDs represents a generalization of the classical gatelevel stuck-at fault model to higher levels -the latter was defined for Boolean expressions whereas the former is defined for nodes in HLDDs having more general interpretation.

Multi-level fault simulation of digital systems on decision diagrams

Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002

A new method for hierarchical fault simulation based on multi-level Decision Diagrams (DD) is proposed. We suppose that a register transfer (RT) level information along with gate-level descriptions for blocks of the RT level structure are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits at these representation levels. The approach proposed allows to reduce time expenses in the comparison to traditional gate-level fault simulation approach.

Hierarchical Fault Simulation in Digital Systems

A new method for hierarchical fault simulation based on multilevel Decision Diagrams (DD) is proposed. We suppose that a register transfer level (RTL) information along with gate-level descriptions for blocks of the RTL structure are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits at these representation levels. The approach proposed allows to reduce time expenses in the comparison to traditional gate-level fault simulation approach. This is reflected in the experimental results.

Diagnostic reasoning in digital systems

[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers

Described in this thesis is an efficient method for fault diagnosis in digital systems based on the technique of reasoning. The methodology operates on the observed erroneous behavior and the structure of the system. The behavior consists of the error(s) observed on the circuit's output lines and specific values on the circuit's input lines. The techniques described in this thesis improve upon previously published research on diagnostic reasoning in two ways. Previous work has stressed system independent techniques which could be used to diagnose any faulty system whose structure can be represented. By concentrating on the specific case of diagnosing faulty digital circuits, it is possible to simplify the representation of the structure of the system. This representation, in the form of an AND/OR fault tree, efficiently abstracts the structure of a faulty digital system. More importantly, a method for partitioning the digital system is introduced which can considerably reduce the runtime complexity of a diagnosis.

High-Level Modeling and Testing of Multiple Control Faults in Digital Systems

— A new method for high level fault modeling to improve the test generation for the control parts of digital systems was proposed. We developed a new high-level functional fault model based on High-Level Decision Diagrams (HLDD). It allows uniform handling of possible defects in different control functions related to instruction decoding, data addressing, and data manipulation. It was shown how the proposed high-level fault model can be mapped on the low-level faults of a joint class of stuck-at faults (SAF), conditional SAF and bridging faults. We proposed uniform procedures for high-level fault activation as a graph traversing procedure on HLDDs related to selection of control signals, and for fault propagation as a task of solving data constraints without using implementation details. Experimental results demonstrated that combining both, high-level control fault reasoning and low-level test generation for data part of a system can help to achieve higher fault coverage and detection of redundant faults than using low-level test generation approach alone.

Hierarchical Test Generation with Multi-Level Decision Diagram Models

1998

A hierarchical test generation approach to digital circuits that uses Register-Transfer (RT) and gate level information as input is presented. The proposed test generator implements a novel approach based on Decision Diagram (DD) models. Uniform modeling procedures are used on both levels, as well as for datapath and control parts. Experimental results showing the efficiency of the approach and comparison with other approaches are provided.

Multiple Fault Testing in Systems-on-Chip with High-Level Decision Diagrams

—A new method of high level test generation based on the concept of test groups to prove the correctness of a part of system functionality is proposed. High-level faults of any multiplicity are assumed to be present in the system, however, there will be no need to enumerate them. Unlike the known approaches, we do not target the faults as test objectives. The goal of using the test groups is to extend step by step the fault-free core of the system by exploiting the knowledge about already successfully tested parts of the system. In case when the proof fails, fault diagnosis will follow. To cope with the complexity of multiple fault masking mechanisms, high-level decision diagrams (HLDD) are used. The proposed method can be regarded as a generalization of the logic level test pair approach for identifying fault-free wires in gate-level networks. Preliminary experimental results, and a discussion of the complexity of the method is presented.

Hierarchical Modelling and Diagnosis for Embedded Systems

Fault Detection, Supervision and Safety of Technical Processes 2006, 2007

Because of the increasing complexity of engineered systems, abstractions and hierarchies in models are receiving great attention. The behaviour of embedded systems is commonly characterised by hybrid phenomena in which each operational mode is activated by electronic units: it hence involves hardware and software components. The aim of this work is to apply a multimodelling approach on such systems for the diagnosis task. This is illustrated by an example taken from the automotive domain.