Diagnostic Modelling of Digital Systems with Multilevel Decision Diagrams (original) (raw)
2000
To cope with the complexity of today's digital systems in diagnostic modelling, hierarchical approaches should be used. In this paper, the possibilities of using Decision Diagrams (DD) for diagnostic modelling of digital systems are discussed. DDs can be used for modelling systems at different levels of representation like logic level, register transfer level, instruction set level. The nodes in DDs
Related papers
High-Level Modeling and Testing of Multiple Control Faults in Digital Systems
— A new method for high level fault modeling to improve the test generation for the control parts of digital systems was proposed. We developed a new high-level functional fault model based on High-Level Decision Diagrams (HLDD). It allows uniform handling of possible defects in different control functions related to instruction decoding, data addressing, and data manipulation. It was shown how the proposed high-level fault model can be mapped on the low-level faults of a joint class of stuck-at faults (SAF), conditional SAF and bridging faults. We proposed uniform procedures for high-level fault activation as a graph traversing procedure on HLDDs related to selection of control signals, and for fault propagation as a task of solving data constraints without using implementation details. Experimental results demonstrated that combining both, high-level control fault reasoning and low-level test generation for data part of a system can help to achieve higher fault coverage and detection of redundant faults than using low-level test generation approach alone.
Multiple Fault Testing in Systems-on-Chip with High-Level Decision Diagrams
—A new method of high level test generation based on the concept of test groups to prove the correctness of a part of system functionality is proposed. High-level faults of any multiplicity are assumed to be present in the system, however, there will be no need to enumerate them. Unlike the known approaches, we do not target the faults as test objectives. The goal of using the test groups is to extend step by step the fault-free core of the system by exploiting the knowledge about already successfully tested parts of the system. In case when the proof fails, fault diagnosis will follow. To cope with the complexity of multiple fault masking mechanisms, high-level decision diagrams (HLDD) are used. The proposed method can be regarded as a generalization of the logic level test pair approach for identifying fault-free wires in gate-level networks. Preliminary experimental results, and a discussion of the complexity of the method is presented.
Loading Preview
Sorry, preview is currently unavailable. You can download the paper by clicking the button above.