Digital VLSI implementation of a neural processor (original) (raw)

VLSI architectures for neural networks

IEEE Micro, 1989

An introduction to neural networks and neural information processing is provided. Neurocomputers are discussed, focusing on how their design exploits the architectural properties of VLSI circuits. General-purpose and special-purpose neurocomputer developments throughout the world are examined. As illustration, and to put European developments in perspective, some of the important projects in the United States and Japan are described. European research is then discussed in greater detail.>

VLSI implementation of neural networks

International Journal of Neural Systems, 2000

Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more complex and hard to train, but provide an outstanding control surface with much less error than that of a fuzzy controller. There are also some problems that have to be solved before the networks can be implemented on VLSI chips. First, an approximation function needs to be developed because CMOS neural networks have an activation ...

VLSI IMPLEMENTATION OF BACK PROPAGATED NEURAL NETWORK FOR SIGNAL PROCESSING

TJPRC, 2014

Mainly due to the rapid advances in integration technologies, large-scale systems design - in short, due to the advent of VLSI Technology, the number of applications of integrated circuits in high-performance computing, telecommunications, and consumer electronics has been rising steadily, and at a very fast pace. Typically, the required computational power of these applications is the driving force for the fast development of this field. This paper present the implementation of Neural Network for signal processing application using VLSI technology. Gilbert mixer which is a transistorized circuit used as an analog multiplier and Adder of Nural Network. The advantage of this circuit is the output current is an accurate multiplication of the (differential) base currents of both inputs. As a mixer, its balanced operation, cancels out many unwanted mixing products, resulting in a "cleaner" output. Through the proposed Neural Network, Compresson & Decompression of two analog signals successfully implemented. Effort has been taken to design Neural Network for signal processing, using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD and practical experience in layout design. The proposed mixer is designed using 45 nm CMOS/VLSI technology with microwind 3.1.

Artificial Neural Network architecture and hardware Chip Implementation using VHDL

International Journal of Advance Research, Ideas and Innovations in Technology, 2019

Artificial neural networks are extended on the basis of brain structure. Like the brain, ANNs can recognize patterns, handle facts and figures and be trained. They are prepared by artificial neurons which employ the quintessence of genetic neurons. In the research work, we have considered the 8 inputs ANN signal which is multiplied with their corresponding weights. The hardware chip is designed to support the system functionality in Xilinx ISE 14.2 software. The designed chip is simulated with Modelsim 10.0 software for test cases. The designed chip is also synthesized on SPARTAN-3E FPGA using VHDL programming and device hardware and timing parameters are also analyzed for the functionality of the chip.

A Pattern Recognition Demonstrator based on a Silicon Neural Chip

Colloids and Surfaces B-biointerfaces, 1992

This paper describes a self-standing hardware pattern recognition system based on neural algorithms. The system uses a dedicated VLSI neural chip which implements a vector-matrix multiplier built of an array of 16 �? 8 multiplying D/A converters with an 8-bit digital storage cell each. The conversion principle is based on an aperiodic clock which rotates data through a weighting shift