Test pattern generation for analog circuits using neural networks and evolutive algorithms (original) (raw)
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1998 IEEE AUTOTESTCON Proceedings. IEEE Systems Readiness Technology Conference. Test Technology for the 21st Century (Cat. No.98CH36179), 1998
Are fault simulation techniques feasible and e ective for fault diagnosis of analog circuits ? In this paper, we investigate these issues via a software tool which can generate testability metrics and diagnostic information for analog circuits represented by SPICE descriptions. This tool, termed the Virtual Test-Bench (VTB), incorporates three di erent simulation-based techniques for fault detection and isolation. The rst method is based on the creation of fault-test dependency models, while the other two techniques employ machine learning principles based on the concepts of: (1) Restricted Coloumb Energy (RCE) Neural Networks, and (2) Learning Vector Quantization (LVQ). Whereas the output of the rst method can be used for the traditional o -line diagnosis, the RCE and LVQ models render themselves more naturally to on-line monitoring, where measurement data from various sensors is continuously available. Since it is well known that analog faults and test measurements are a ected by component parameter variations, we have also addressed the issues of robustness of our fault diagnosis schemes. Speci cally, we have attempted to answer the questions regarding xing of test measurement thresholds, obtaining the minimum number of Monte-Carlo runs required to stabilize the measurements and their deviations, and the e ect of di erent thresholding schemes on the robustness of fault models. Although fault-simulation is a powerful technique for analog circuit testability analysis, its main shortcomings are the long simulation time, large volume of data and thedelity of simulators in accurately modeling faults. We have plotted the simulation time and volume of data required for a range of circuit sizes to provide guidance on the feasibility and e cacy of this approach.
IJERT-Analog Circuits Testing Using Monte-Carlo Analysis and Neural Networks
International Journal of Engineering Research and Technology (IJERT), 2014
https://www.ijert.org/analog-circuits-testing-using-monte-carlo-analysis-and-neural-networks https://www.ijert.org/research/analog-circuits-testing-using-monte-carlo-analysis-and-neural-networks-IJERTV1IS6092.pdf Analog Circuits testing using Monte Carlo Analysis and Neural Networks is a new technique which is proposed for the diagnosis of fault in Analog Circuits. According to this method, the circuit which is to be tested is supplied with a ramp shape voltage. The output supply current is now analyzed with a new unsupervised neural network. If circuit has any fault then its supply current waveform will change. In this case the waveform of the supply current can be related to the type of the fault. In general to obtain this relationship will be a difficult task, but neural networks can provide a suitable solution for this problem. This network has been used in a hierarchical way. In the first step, a single layer is used to classifies the faults. If a single node represents a few faults then a sub layer is added to classify the other faults. This process will continues until a node represents each fault class according to analysis.
Use of Neural Networks in Testing Analog to Digital Converters
In the past two decades, the techniques of artificial neural networks are growing mature, as a datadriven method, which provides a totally new perspective to fault diagnosis. Testing issues are becoming more and more important with the quick development of both digital and analog circuit industry. Analog-to-digital converters (ADCs) are becoming more and more widespread owing to their fundamental capacity of interfacing analog physical world to digital processing systems. In this paper, we study the use of neural networks in fault diagnosis of ADCs and compare the results with other ADC testing approaches such as histogram, FFT and sine fit test techniques. In this paper, we study the use of neural networks in fault diagnosis of ADCs and compare the results with other ADC testing approaches such as histogram, FFT and sine fit test techniques. In this paper, we introduce two ideas to improve the training phase time. They are separation and indexing of neural network outputs. Finally, we concluded that neural network approach is a robust way for fault diagnosis of ADCs and also other mixed signal circuits.
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This paper deals with approach to analogue circuits functional test. The neural network is used as signature classifier providing detection catastrophic and parametric faults. Wavelet decomposition as preprocessing of circuit’s output responses allows generating the signatures. Using of transient responses gives possibility to keep and take into account the dynamical characteristics of analogue circuits during testing. The experimental results of proposed approach and comparison with other methods are shown.
Corresponding Author: Design and Implementation of Neural Network Based circuits for VLSI testing
Artificial Neural Network (ANN) plays a vital role in biologically inspired microcircuits, which is also known as the new trend of Very Large Scale Integration (VLSI) involvement of silicon based neurons. This paper proposes a new design methodology in VLSI testing using neural network. Hardware based circuit is constructed by utilizing the features of neural network and that circuit is also tested for fault free method. Experimental results are targeted to ISCAS85 Combinational Benchmark circuit. Implementation of proposed fault free circuit is written in VHDL and synthesised with XILINX Spartan III FPGA.
Specification-driven test generation for analog circuits
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2000
In this paper, a new methodology for generating transient tests to detect faults in analog circuits is presented. Relationship between circuit functionalities and physical failures is exploited to derive these tests. These fast transient tests can be used for implicitly verifying the circuit specifications. A fast fault simulation algorithm for linear analog circuits based on state-space representation and adjoint network method is also presented. This fault simulation algorithm is used for generating transient test for linear analog circuits. For nonlinear circuits, an existing circuit simulator is used for test generation. The generated tests are evaluated and found to give low misclassification rates for a large class of analog circuits