The Statistical Failure Analysis for the Design of Robust SRAM in Nano-Scale Era (original) (raw)
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IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2005
In this paper, we have analyzed and modeled failure probabilities (access-time failure, read/write failure, and hold failure) of synchronous random-access memory (SRAM) cells due to process-parameter variations. A method to predict the yield of a memory chip based on the cell-failure probability is proposed. A methodology to statistically design the SRAM cell and the memory organization is proposed using the failure-probability and the yield-prediction models. The developed design strategy statistically sizes different transistors of the SRAM cell and optimizes the number of redundant columns to be used in the SRAM array, to minimize the failure probability of a memory chip under area and leakage constraints. The developed method can be used in an early stage of a design cycle to enhance memory yield in nanometer regime.
Failure analysis for ultra low power nano-CMOS SRAM under process variations
2008 IEEE International SOC Conference, 2008
Several design metrics have been used in the past to evaluate the SRAM cell stability. However, most of them fail to provide the exact stability figures as shown in this paper. Therefore, we investigate new stability metrics and report the stability analysis for typical a SRAM cell. In particular, a concept called power metric is introduced. From this metric we derive two new stability figures; static power noise margin (Ë ÈAE Å ) and write trip power (Ï Ì È ). It is shown that these new figures provide better cell stability analysis. Furthermore, we have exhaustively analyzed the impact of different parameters variations such as cell ratio, supply voltage Î and threshold voltage Î Ø on Ë ÈAE Åand Ï Ì È . Statistical models for estimating Ë ÈAE Å and Ï Ì È from intra-die Î Ø variations are presented. The estimated results match well with the Monte Carlo (MC) simulations.
Trends and challenges of SRAM reliability in the nano-scale era
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2010
According to the International Technology Roadmap for Semiconductors (ITRS), embedded Static Random Access Memory (SRAM) will continue to dominate the area of System on Chips (SoCs) approaching 90% in the next 10 years. Therefore, SRAM reliability will have a significant impact on overall SoC reliability. This paper presents state-of-the-art transistor failure mechanisms and their impact on SRAM reliability parameters including cell stability, cell read failures, and cell access time failures. Furthermore, different techniques currently employed in industry, to mitigate the impacts of the failure mechanisms are presented. Finally, based on the current scaling trends reliability challenges of future transistors and embedded SRAM are discussed. The discussion concludes that the reliability challenges in future embedded SRAM will increase significantly.
Probability calculation of read failures in nano-scaled SRAM cells under process variations
Microelectronics Reliability, 2012
In this paper, we present an accurate method for predicting the read failure probability of SRAM cells. First, using a simple I-V model for transistors, analytical expressions for the V read and V trip of SRAM cells are obtained. These expressions are subsequently used to derive a fairly accurate model for the read margin of SRAM cells. Then, using Jacobian determinant, the joint probability density function for the V read and V trip is calculated without assuming any specific distribution function for its probability. The accuracy of the approach is studied by comparing its results with those of previous techniques and standard Monte Carlo simulations for 32 and 45 nm CMOS technologies. Compared to these techniques, our approach has a considerably lower error at the price of slightly increasing the computation time or is much faster at the cost of marginally decreasing the accuracy. In addition, the method has the advantage of not being restricted to a specific probability distribution form.
Statistical SRAM analysis for yield enhancement
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010
This paper presents an automated technique to perform SRAM wide statistical analysis in presence of process variability. The technique is implemented in a prototype tool and is demonstrated on several 45 and 32nm industry-grade SRAM vehicles. Selected case studies show how this approach successfully captures non-trivial statistical interactions between the cells and the periphery, which remain uncovered when only using statistical electrical simulations of the critical path or applying a digital corner approach. The presented tool provides the designer with valuable information on what performance metrics to expect, if manufactured. Since this feedback takes place in the design phase, a significant reduction in development time and cost can be achieved.
SRAM supply voltage scaling: A reliability perspective
2009 10th International Symposium on Quality Electronic Design, 2009
SRAM leakage power is a significant fraction of the total power consumption on a chip. Traditional SRAM supply voltage scaling reduces the leakage power, but it increases stored-data failure rate (e.g., due to soft-errors). Accordingly, this work studies SRAM leakage power reduction with a data-reliability constraint ensured by system-level design techniques, like error-correction, supply voltage reduction, and data-refresh (scrubbing). A statistical or probabilistic setup is used to model failure mechanisms like soft-errors or process-variations, and error-probability is used as a metric for data-failure rate. Error models which combine various SRAM cell failure mechanisms are developed. Using these error-models, system level optimization of leakage power constrained by a constant data error-probability requirement is studied. Circuit-level simulation results and leakage power reduction estimates for the CMOS 90nm technology are presented.
2005
As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes Step-Stress techniques to evaluate memory technologies (0.25um, 0.15um, and 0.13um) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.
A yield-aware modeling methodology for nano-scaled SRAM designs
2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005., 2005
In this paper. a modeting methodology to maximize the yield of a SRAM memory array is presented. The method is robust to process variations. Calibrated models for the distributions of performance parameters are used to predict the sensitivity of the design performance to variability. The calibration and the verification of the prediction are based on 130nm devices. Projection to future nano-scaled technology nodes indicates that further scaling requires good modeling of the parametric variations to overcome poor yield, unless the variations can he better controlled.
Microelectronics Reliability, 2012
This paper presents a technique for designing a variability aware SRAM cell. The architecture of the proposed cell is similar to the standard 6T SRAM cell with the exception that the access pass gates are replaced with full transmission gates. The paper studies the impact of V t (threshold voltage) variation on most of the design metrics of SRAM cell. The proposed design achieves 1.4Â narrower spread in I READ at the expense 1.2Â lower I READ at nominal V DD . It offers 1.3Â improvements in T RA (read access time) distribution at the expense of 1.2Â penalty in read delay. The proposed bitcell offers 1.1Â tighter spread in T WA (write access time) incurring 1.3Â longer write delay. It shows 180 mV of SNM (static noise margin) and is equally stable in hold mode. It offers 1.3Â higher RSNM (100 mV) compared to 6T (75 mV). It exhibits improved SINM (static current noise margin) distribution at the expense of 1.6Â lower WTI (write trip current). It offers 1.05Â narrower spread in standby power. Thus, comparative analysis based on Monte Carlo simulation exhibits that the proposed design is capable of mitigating impact of V t variation to a large extent.
Journal of Nanostructures, 2021
Nano scale statistical variability which arises from discreteness of charge and granularity of matter has become one of major concerns in digital design particularly in sub-50nm technology nodes. Device intrinsic parameters such as the threshold voltage and drive current will be influenced by random dopants, line edge roughness and gate grain granularity which in turn results in variation of SRAM cell performance. Therefore, providing an accurate statistical model is one of the key issues among SRAM design community. Since both 6T and 8T SRAMs are widely used in the industry as standard cells, this article analyzes sensitivity of static noise margin (SNM) in response to statistical variations in 6-and 8-transistor cells. The results show that though 8T cells need more transistors and thus consume more area on the wafer compared with 6T cells, they are more stable and thus are better candidates for variability aware design in future technology nodes.