Soft Error Tolerance in Memory Applications (original) (raw)
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Design of Majority Logic Decoder for Error Detection and Correction in Memories
Due to augmenting integration densities, technology scaling and variation in parameters, the performance failures would possibly occur for every application. The memory applications are vulnerable to single event upsets and transient errors which may cause malfunctions. This paper deals with the idea of a totally distinctive fault detection and correction technique using EG-LDPC codes with the applying mainly targeted on reminiscences. The majority logic secret writing is used here, since it will correct associate degree outsize type of errors. Albeit the majority secret writing consumes longer, it will be overcome by the projected technique that detects the errors in less cycle time. It will clearly reduce operation time once the information scan technique is error free. the employment of associate degree additional logic finishes up during a little house overhead in projected methodology once place next to the current technique, that's overcome by a revised implementation of majority gate.
Efficient Majority Logic Fault Detection in Memory Applications with Difference-Set Codes
Even a small transition delays and little faults create major concern in digital circuits. It Produce greater impact on not only for simple memory but also for most of the memory applications. This paper presents an error-detection method for difference-set cyclic codes with majority logic decoding. Majority logic decodable codes are suitable for memory applications due to their capability to correct a large number of errors. However, they require a large decoding time that impacts memory performance. The proposed fault-detection method significantly reduces memory access time when there is no error in the data read. The technique uses the majority logic decoder itself to detect failures, which makes the area overhead minimal and keeps the extra power consumption low. The proposed method detects the occurrences of single error, double error ,triple error in the received code words obtained from the memory system.
Reliability, Availability and Serviceability are the three important parameters to be satisfied by any application. With further reduction in transistor size that leads to smaller dimensions, higher integration densities, and lower operating voltages, the reliability of memories is put into jeopardy. Single event upsets (SEUs) altering digital circuits are becoming a bigger concern for memory applications. An error-detection method for difference-set cyclic codes with majority logic decoding is presented. Majority logic decodable codes are suitable for memory applications due to their capability to correct a large number of errors. They are simple to implement and have modular encoders and decoders. However, they require a large decoding time that impacts memory performance. The proposed fault-detection method significantly reduces memory access time when there is no error in the data read. The technique uses the majority logic decoder itself to detect failures, which makes the area overhead minimal and keeps the extra power consumption low.
Majority Logic Fault Detection with Difference-Set Codes for Memory Applications
Reliability, Availability and Serviceability are the three important parameters to be satisfied by any application. With further reduction in transistor size that leads to smaller dimensions, higher integration densities, and lower operating voltages, the reliability of memories is put into jeopardy. Single event upsets (SEUs) altering digital circuits are becoming a bigger concern for memory applications. An error-detection method for difference-set cyclic codes with majority logic decoding is presented. Majority logic decodable codes are suitable for memory applications due to their capability to correct a large number of errors. They are simple to implement and have modular encoders and decoders. However, they require a large decoding time that impacts memory performance. The proposed fault-detection method significantly reduces memory access time when there is no error in the data read. The technique uses the majority logic decoder itself to detect failures, which makes the area overhead minimal and keeps the extra power consumption low.
Matrix Code Based Multiple Error Correction Technique for N-Bit Memory Data
International Journal of VLSI Design & Communication Systems, 2013
Constant shrinkage in the device dimensions has resulted in very dense memory cells. The probability of occurrence of multiple bit errors is much higher in very dense memory cells. Conventional Error Correcting Codes (ECC) cannot correct multiple errors in memories even though many of these are capable of detecting multiple errors. This paper presents a novel decoding algorithm to detect and correct multiple errors in memory based on Matrix Codes. The algorithm used is such that it can correct a maximum of eleven errors in a 32-bit data and a maximum of nine errors in a 16-bit data. The proposed method can be used to improve the memory yield in presence of multiple-bit upsets. It can be applied for correcting burst errors wherein, a continuous sequence of data bits are affected when high energetic particles from external radiation strike memory, and cause soft errors. The proposed technique performs better than the previously known technique of error detection and correction using Matrix Codes.
Modifying Hamming code and using the replication method to protect memory against triple soft errors
TELKOMNIKA Telecommunication Computing Electronics and Control, 2020
As technology scaling increases computer memory’s bit-cell density and reduces the voltage of semiconductors, the number of soft errors due to radiation induced single event upsets (SEU) and multi-bit upsets (MBU) also increases. To address this, error-correcting codes (ECC) can be used to detect and correct soft errors, while x-modular-redundancy improves fault tolerance. This paper presents a technique that provides high error-correction performance, high speed, and low complexity. The proposed technique ensures that only correct values get passed to the system output or are processed in spite of the presence of up to three-bit errors. The Hamming code is modified in order to provide a high probability of MBU detection. In addition, the paper describes the new technique and associated analysis scheme for its implementation. The new technique has been simulated, evaluated, and compared to error correction codes with similar decoding complexity to better understand the overheads required, the gained capabilities to protect data against three-bit errors, and to reduce the misdetection probability and false-detection probability of four-bit errors.
Unidirectional byte error detecting codes for computer memory systems
IEEE Transactions on Computers, 1990
Abslmct-Codes are developed for detecting unidirectional errors in t bytes simultaneously ( t-UBED) while also providing all unidirectional error detection (AUED). These classes of codes differ from purely all unidirectional error detecting codes in that the errors in one byte may be of the form 1 -0 while in another byte they may be of the form 0 + 1. The codes utilize two bytes for parity check information. As an example, a code providing 3-UBED+AUED protection for up to 12 information bytes of 8 bits each can be constructed.
Code Constructions for Error Control in Byte Organized Memory Systems
IEEE Transactions on Computers, 2000
Error correcting codes, such as Hamming codes, have been used successfully to correct errors arising from failures in computer memories. Failure of a chip or card can cause errors which exceed the capabilities of these codes. We construct codes which detect any byte error and correct such errors if they are single random errors.
Programmable extended SEC-DED codes for memory errors
29th VLSI Test Symposium, 2011
Redundant memory columns are an essential ingredient of memory design for yield and reliability. They are used either as spare columns for the replacement of completely defective regular columns or to store check-bits for error detection and correction codes. Column replacement allows to mask isolated malfunctioning storage cells as well. Unfortunately, the number of columns with defective storage cells that can be masked in this way cannot exceed the number of spare columns which is usually quite low. Here, we propose a way to increase the capacity of masking memory columns with isolated defective storage cells using spare memory columns. For this purpose, single error correction and double error detection (SEC-DED) codes already available for the protection against soft errors are extended such that all double-bit errors which affect a fixed sub-set of bit positions in the code words can be corrected. The cardinality of this sub-set is significantly higher than the number of spare columns. A bit-swapper is employed to map the bit positions that are protected by the extended SEC-DED code against double-bit errors to the memory columns with defective storage cells. In this way, single-bit soft-errors affecting any bit position can be corrected simultaneously with single-bit hard errors induced by any subset of memory columns. The bit-swapper can be dynamically reconfigured based on status information that designates the memory columns with defective storage cells. This facilitates the integration into built-in self-repair (BISR) schemes.
IJERT-A Proficient Method of Error Detection Using Ml Algorithm for Memory Applications
International Journal of Engineering Research and Technology (IJERT), 2013
https://www.ijert.org/a-proficient-method-of-error-detection-using-ml-algorithm-for-memory-applications https://www.ijert.org/research/a-proficient-method-of-error-detection-using-ml-algorithm-for-memory-applications-IJERTV2IS101029.pdf As technology scales the size of the memory used in digital circuits are gradually increasing and memory is responsible for storing and retrieving the data which makes its role very essential. The influence of technology mounting smaller dimensions and lower operating voltages have come to a level that consistency of memories is put into risk, not only in dangerous radiation environments like spacecraft and avionics electronics, but also at normal terrestrial environments. Due to higher integration densities, technology scaling and variation in parameters, performance failures may occur. The memory applications are also prone to single event upsets (SEU) and transient errors which may lead to malfunctions. The proposed error-detection method uses ML algorithm and a special class of Low Density Parity Check (LDPC) codes especially Euclidean geometry Codes (EG) which significantly reduces memory access time when there is no error in the data read.