IJERT-Design of Low Power, Area-Efficient Carry Select Adder (original) (raw)

Design of Low Power, Area-Efficient Carry Select Adder

Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is designed by using single Ripple Carry Adder(RCA) and Binary to Excess-1 Converter (BEC) instead of dual RCAs in order to reduce the area and power consumption with small speed penalty. CSA and MCSA structures are designed for 8-bit, 16-bit, 32bit and 64-bit. Result analysis shows that MCSA is better than CSA.

IMPLEMENTATION OF LOW-POWER AND AREA-EFFICIENT 64BIT CARRY SELECT ADDER

Now a day’s hottest area of research in VLSI system is design of the area, high-speed and power-efficient data path logic systems. All processor consisting of Arithmetic & logical Unit (ALU) and adder plays an important role for design of ALU. In digital adders, the speed of addition is limited by the time required to send a carry through the adder. Carry Select Adder (CSLA) is an efficient is used for data-processing processors to perform fast arithmetic functions. The proposed work reduces area and power consumption to a great extent with the help of a simple ripple carry adder (RCA) and gate-level architecture. Regular CSLA consist of two RCA and proposed design has been projected by single RCA. This improves the performance of the proposed designs then the regular designs in terms of power consumption and area.

IJERT-Low-Power and Area-Efficient Carry Select Adder

International Journal of Engineering Research and Technology (IJERT), 2013

https://www.ijert.org/low-power-and-area-efficient-carry-select-adder https://www.ijert.org/research/low-power-and-area-efficient-carry-select-adder-IJERTV2IS120617.pdf Design of power-efficient and high-speed data path logic systems are one of the most substantial areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. The CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input, then the final sum and carry are selected by the multiplexers (mux). The basic idea of this work is to use Binary to Excess-1 Converter (BEC) instead of RCA in the regular CSLA to achieve high speed and low power consumption.

ENHANCED LOW POWER, FAST AND AREA EFFICIENT CARRY SELECT ADDER

Adder being the basic hardware block of any arithmetic operation, the major constraint in the field of signal processors, data processors to perform any operations is highly dependent on the adder performance of the circuit. The gate level implementation of the carry select adder (CSLA) and modified carry select adder has significantly reduced the area and power consumption which replaced the ripple carry adder (RCA) used in modified CSLA with MUX based Full Adder (MUX-FA) block has further reduced the power consumption by efficiently utilizing the area with faster performance.

A Novel Approach OF Low Power and Area Efficient Carry Select Adder

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only as light increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-m CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

Implementation of Low Power and Area-Efficient Carry Select Adder

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32- ,-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-m CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

Design of 32-bit Carry Select Adder with Reduced Area

International Journal of Computer Applications, 2013

Addition is the heart of arithmetic unit and the arithmetic unit is often the work horse of a computational circuit. So adders play a key role in designing an arithmetic unit and also many digital integrated circuits. Carry Select Adder (CSLA) is one of the fastest adders used in many data processors and in digital circuits to perform arithmetic operations. But CSLA is area-consuming because it consists of dual ripple carry adder (RCA) in the structure. To reduce the area of CSLA, a CSLA with Binary to Excess-1 Converter is already designed which reduces the area of adder. But there are other techniques to design a CSLA to reduce its area. One of such technique is using an add one circuit technique. This paper proposes the design of square root CSLA (SQRT CSLA) using add one circuit with significant reduction in area. The proposed design is synthesized using Leonardo Spectrum to get area (number of gates) and delay (ns). The performance in terms of area and delay are evaluated for square root CSLA using add one circuit and are compared with existing SQRT CSLA and SQRT CSLA using Binary to Excess-1 Converter (BEC). The results analysis shows that the proposed SQRT CSLA using add one circuit is better than the existing SQRT CSLA and SQRT CSLA using BEC.

Low-Power and Area-Efficient Carry Select Adder

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-m CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

PERFORMANCE AND ANALYSIS OF LOW POWER, AREAEFFICIENT AND HIGH SPEED CARRYFAST ADDER

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8, 16,32,and 64-bit square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power. Binary to Excess-1 Converter (BEC) instead of RCA with the regular CSLA to achieve lower area and power consumption. The main advantage of this BEC logic comes from the lesser number of logic gates than the n-bit Full Adder structure. The delay and area evaluation methodology of the basic adder blocks. The SQRT CSLA has been chosen for comparison with the proposed design as it has a more balanced delay, and requires lower power and area. Reducing the area and power consumption in the CSLA. Efficient gate-level modification to significantly reduce the area and powerof the CSLA.

IJERT-A New Architecture Designed for Implementing Area Efficient Carry-Select Adder

International Journal of Engineering Research and Technology (IJERT), 2016

https://www.ijert.org/a-new-architecture-designed-for-implementing-area-efficient-carry-select-adder https://www.ijert.org/research/a-new-architecture-designed-for-implementing-area-efficient-carry-select-adder-IJERTV5IS030262.pdf In this work, We have analyze the Conventional Carry Select Adder (CSLA) and Binary to Excess-1 converter (BEC) based CSLA contained logic operations and recognize the superfluous logic operations. The conventional CSLA contained superfluous logic operations are removed and introduce new logic operations for carry select adder. The carry select (CS) operation is performed before the calculation of final sum in newly introduced logic operations. We modify the design of carry select adder using newly introduced logic operations based logic units. From the synthesis results, the modified structure of CSLA yields significantly less area than the conventional CSLA and BEC-based CSLA. Due to the small carry-output delay, the modified CSLA design is best suitable for square-root (SQRT) CSLA.